3.2 Idle Mode

In idle mode, the Cortex-M3 is in deep-sleep after executing the WFI instruction. The Cortex-M3 waits for interrupts to wake up. The CPU power domain is off to reduce the current consumption. The CPU power domain increases the wake-up time of approximately 25 µs. Consider this increase if the application is timing sensitive. Although the CPU power domain is off, it retains its contents. When waking up from idle mode, the Cortex-M3 resumes executing code at the point it left off before entering idle. The state and register contents of the Cortex-M3 remain unchanged.

In idle mode, the application program can use system resources, including the high-speed crystal oscillator, the radio, and the peripherals. The Cortex-M3 can wake up from any enabled interrupt source. For details on entering idle mode, see Figure 1.

The code for entering idle mode is from the TI-RTOS implementation. Find it at the following path: C:\ti\tirtos_cc13xx_cc26xx_#_##_##_##\products\tidrivers_cc13xx_cc26xx_#_##_##_##\packages\ti\drivers\power\PowerCC26XX_tirtos.c.

Figure 1. Idle Enter Sequence

1. Configure flash to remain on in IDLE or not– The flash can remain on to support DMA transactions from flash or if the RF core must access the flash. If the application requires the flash to remain available while in idle, set the PRCM:PDCTL1 bit (see CC13x0, CC26x0 Technical Reference Manual) before entering idle. If the application does not require flash access while in idle, clear this bit for the lowest power consumption.
2. Always keep Cache retention on in idle– Always enable the cache retention to ensure faster start-up time and easier software implementation. The current consumption caused by retaining the cache in idle is negligible compared to the total idle current consumption.
3. Turn off the CPU power domain– Ensure the CPU power domain is off when the Cortex-M3 enters deep-sleep. The CPU power domain is turned off after the Cortex-M3 executes the WFI instruction (with the NVIC SLEEP_DEEP bit set) and enters deep-sleep.
4. Ensure any possible outstanding AON writes are completed– If the AON domain has any outstanding writes, the driver must ensure they complete before entering idle. This function call stalls the Cortex-M3 execution for up to one SCLK_LF period because the AON domain runs on the SCLK_LF.
5. Enter IDLE— Put the Cortex-M3 in deep-sleep through the WFI instruction to enter idle. If the wake-up source is the RTC, the software must perform AON synchronization (in Step 4) before reading from the RTC module to ensure the RTC values are updated correctly.