SWRA751 September 2022
Description:
This command configures the codec interface parameters and the PCM clock rate, which is relevant when the Bluetooth core generates the clock. This command must be used by the host to use the PCM interface.
| Command Parameter | Size (bytes) | Value | Description |
|---|---|---|---|
| Clock rate | 2 | 64-16,000 | The PCM clock rate in KHz. Valid values are between 64K to 4096K (for master mode) or 64K to 16M (for slave mode). It influences other parameters such as wait cycles and frequency rate calculation and therefore must be configured even if an external clock is used. |
| Clock direction | 1 |
0x00 0x01 |
PCM clock and Fsync direction is output (codec_IF is Master on PCM bus) and sampled on rising edge PCM clock and Fsync direction is input |
| Frame-sync frequency | 4 | 100 Hz – 173 kHz | Frame-sync frequency in Hz |
| Frame-sync duty cycle | 2 |
0x0000 0x0001-0xFFFF |
50% of Fsync period (I2S Format) Number of cycles of PCM clock |
| Frame-sync edge | 1 |
0x00 0x01 |
Driven/sampled at rising edge of the PCM clock Driven/sampled at falling edge of the PCM clock |
| Frame-sync polarity | 1 |
0x00 0x01 |
Active high Active low |
| Reserved | 1 | ||
| Channel 1 data out size | 2 | 0x0001 – 0x0280 | Sample size in bits for each
codec Fsync The value is between 1 bit and 0x0280 bits. If data size is greater than 24 bits, the size must be divisible by 8 (for example, 1–24,32, 40, 48, etc.). |
| Channel 1 data out offset | 2 | 0x0000 – 0x00FF | Number of PCM clock cycles between rising of frame sync and data start. NOTE:Please note that the offset of CH2 must be a minimum of CH1 DATA LENGHT + 1.This requirement is important also when CH2 is not used. |
| Channel 1 data out edge | 1 |
0x00 0x01 |
Data driven at rising edge of the PCM clock Data driven at falling edge of the PCM clock |
| Channel 1 data in size | 2 | 0x0001 – 0x0280 | Sample size in bits for each
codec Fsync The value is between 1 bit and 0x0280 bits. If data size is greater than 24 bits, the size must be divisible by 8 (for example, 1–24,32, 40, 48, etc.). |
| Channel 1 data in offset | 2 | 0x0000 – 0x00FF | Number of PCM clock cycles between rising of frame sync and data start |
| Channel 1 data in edge | 1 | 0x000x01 | Data sampled at rising edge of
the PCM clock Data sampled at falling edge of the PCM clock |
| Fsynch Multiplier | 1 |
0x00/0xFF 32/64 |
This field is only relevant
to CC256XB from SP 0.2 !!! When setting the values 0x00 or 0xFF the command will act the same as previously, but when entering a value of 32/64 the Clock Rate will be: Clock Rate = Fsynch Multiplier X Frame Synch frequency , for example 44,100Hz X 32 = 1441,200Hz |
| Channel 2 data out size | 2 | 0x0001 – 0x0280 | Sample size in bits for each
codec Fsync The value is between 1 bit and 0x0280 bits. If data size is greater than 24 bits, the size must be divisible by 8 (for example, 1–24,32, 40, 48, etc.). |
| Channel 2 data out offset | 2 | 0x0000 – 0x00FF | Number of PCM clock cycles between rising of frame sync and data start. NOTE:Please note that the offset of CH2 must be a minimum of CH1 DATA LENGHT + 1.This requirement is important also when CH2 is not used. |
| Channel 2 data out edge | 1 |
0x00 0x01 |
Data driven at rising edge of the PCM clock Data driven at falling edge of the PCM clock |
| Channel 2 data in size | 2 | 0x0001 – 0x0280 | Sample size in bits for each
codec Fsync The value is between 1 bit and 0x0280 bits. If data size is greater than 24 bits, the size must be divisible by 8 (for example, 1–24,32, 40, 48, etc.). |
| Channel 2 data in offset | 2 | 0x0000 – 0x00FF | Number of PCM clock cycles between rising of frame sync and data start |
| Channel 2 data in edge | 1 | 0x000x01 | Data sampled at rising edge of
the PCM clock Data sampled at falling edge of the PCM clock |
| Reserved | 1 |
| Returned Value | Description | Size (bytes) | Events Generated |
|---|---|---|---|
| 0x00 0x01 – 0xFF |
Command succeeded. Command failed. |
1 | Command Complete |