SWRS121E July   2012  – January 2016 CC2560 , CC2560B , CC2564

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Attributes
    2. 4.2 Connections for Unused Signals
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
      1. 5.1.1 ESD Ratings
      2. 5.1.2 Power-On Hours
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power Consumption Summary
      1. 5.3.1 Static Current Consumption
      2. 5.3.2 Dynamic Current Consumption
        1. 5.3.2.1 Current Consumption for Different Bluetooth BR/EDR Scenarios
        2. 5.3.2.2 Current Consumption for Different LE Scenarios
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing and Switching Characteristics
      1. 5.5.1 Device Power Supply
        1. 5.5.1.1 Power Sources
        2. 5.5.1.2 Device Power-Up and Power-Down Sequencing
        3. 5.5.1.3 Power Supplies and Shutdown - Static States
        4. 5.5.1.4 I/O States in Various Power Modes
        5. 5.5.1.5 nSHUTD Requirements
      2. 5.5.2 Clock Specifications
        1. 5.5.2.1 Slow Clock Requirements
        2. 5.5.2.2 External Fast Clock Crystal Requirements and Operation
        3. 5.5.2.3 Fast Clock Source Requirements (-40°C to +85°C)
      3. 5.5.3 Peripherals
        1. 5.5.3.1 UART
        2. 5.5.3.2 PCM
      4. 5.5.4 RF Performance
        1. 5.5.4.1 Bluetooth BR/EDR RF Performance
          1. 5.5.4.1.1 Bluetooth Receiver—In-Band Signals
          2. 5.5.4.1.2 Bluetooth Receiver—General Blocking
          3. 5.5.4.1.3 Bluetooth Transmitter—GFSK
          4. 5.5.4.1.4 Bluetooth Transmitter—EDR
          5. 5.5.4.1.5 Bluetooth Modulation—GFSK
          6. 5.5.4.1.6 Bluetooth Modulation—EDR
          7. 5.5.4.1.7 Bluetooth Transmitter—Out-of-Band and Spurious Emissions
        2. 5.5.4.2 Bluetooth LE RF Performance
          1. 5.5.4.2.1 BLE Receiver—In-Band Signals
          2. 5.5.4.2.2 BLE Receiver—General Blocking
          3. 5.5.4.2.3 BLE Transmitter
          4. 5.5.4.2.4 BLE Modulation
          5. 5.5.4.2.5 BLE Transceiver, Out-Of-Band and Spurious Emissions
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Clock Inputs
      1. 6.3.1 Slow Clock
      2. 6.3.2 Fast Clock Using External Clock Source
        1. 6.3.2.1 External FREF DC-Coupled
        2. 6.3.2.2 External FREF Sine Wave, AC-Coupled
        3. 6.3.2.3 Fast Clock Using External Crystal
    4. 6.4 Functional Blocks
      1. 6.4.1 RF
        1. 6.4.1.1 Receiver
        2. 6.4.1.2 Transmitter
      2. 6.4.2 Host Controller Interface
        1. 6.4.2.1 4-Wire UART Interface—H4 Protocol
        2. 6.4.2.2 3-Wire UART Interface—H5 Protocol (CC2560B and CC2564B Devices)
      3. 6.4.3 Digital Codec Interface
        1. 6.4.3.1 Hardware Interface
        2. 6.4.3.2 I2S
        3. 6.4.3.3 Data Format
        4. 6.4.3.4 Frame Idle Period
        5. 6.4.3.5 Clock-Edge Operation
        6. 6.4.3.6 Two-Channel Bus Example
        7. 6.4.3.7 Improved Algorithm For Lost Packets
        8. 6.4.3.8 Bluetooth and Codec Clock Mismatch Handling
      4. 6.4.4 Assisted Modes (CC2560B and CC2564B Devices)
        1. 6.4.4.1 Assisted HFP 1.6 (WBS)
        2. 6.4.4.2 Assisted A2DP
          1. 6.4.4.2.1 Assisted A2DP Sink
          2. 6.4.4.2.2 Assisted A2DP Source
    5. 6.5 Bluetooth BR/EDR Features
    6. 6.6 Bluetooth LE Description
    7. 6.7 Bluetooth Transport Layers
    8. 6.8 Changes from CC2560A and CC2564 to CC2560B and CC2564B Devices
  7. 7Applications, Implementation, and Layout
    1. 7.1 Reference Design Schematics and BOM for Power and Radio Connections
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
    3. 8.3 Related Links
    4. 8.4 Community Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 mrQFN Mechanical Data
    2. 9.2 Packaging and Ordering
      1. 9.2.1 Package and Ordering Information
      2. 9.2.2 Empty Tape Portion
      3. 9.2.3 Device Quantity and Direction
      4. 9.2.4 Insertion of Device
      5. 9.2.5 Tape Specification
      6. 9.2.6 Reel Specification
      7. 9.2.7 Packing Method
      8. 9.2.8 Packing Specification
        1. 9.2.8.1 Reel Box
        2. 9.2.8.2 Reel Box Material
        3. 9.2.8.3 Shipping Box
        4. 9.2.8.4 Shipping Box Material

4 Terminal Configuration and Functions

Figure 4-1 shows the bottom view of the pin attributes.

CC2560A CC2560B CC2564 CC2564B SWRS121-002.gif
Figure 4-1 Pin Diagram (Bottom View)

4.1 Pin Attributes

Table 4-1 describes the pin attributes.

Table 4-1 Pin Attributes

NAME NO. PULL AT RESET DEF. DIR.(1) I/O
Type(2)		 DESCRIPTION
I/O Signals
HCI_RX A26 PU I 8 mA HCI universal asynchronous receiver/transmitter (UART) data receive
HCI_TX A33 PU O 8 mA HCI UART data transmit
HCI_RTS A32 PU O 8 mA HCI UART request-to-send
The host is allowed to send data when HCI_RTS is low.
HCI_CTS A29 PU I 8 mA HCI UART clear-to-send
The CC256x device is allowed to send data when HCI_CTS is low.
AUD_FSYNC A35 PD I/O 4 mA pulse-code modulation (PCM) frame-sync signal Fail-safe
AUD_CLK B32 PD I/O HY, 4 mA PCM clock Fail-safe
AUD_IN B34 PD I 4 mA PCM data input Fail-safe
AUD_OUT B33 PD O 4 mA PCM data output Fail-safe
TX_DBG B24 PU O 2 mA TI internal debug messages. TI recommends leaving an internal test point.
Clock Signals
SLOW_CLK A25 I 32.768-kHz clock in Fail-safe
XTALP/FREFP B4 I Fast clock in analog (sine wave)
Output terminal of fast-clock crystal		 Fail-safe
XTALM/FREFM A4 I Fast clock in digital (square wave)
Input terminal of fast-clock crystal		 Fail-safe
Analog Signals
BT_RF B8 I/O Bluetooth RF I/O
nSHUTD A6 PD I Shutdown input (active low)
Power and Ground Signals
VDD_IO A17, A34, A38, B18, B19, B21, B22, B25 I I/O power supply (1.8-V nominal)
MLDO_IN B5 I Main LDO input
Connect directly to battery
MLDO_OUT A5, A9, B2, B7 I/O Main LDO output (1.8-V nominal)
CL1.5_LDO_IN B6 I Power amplifier (PA) LDO input
Connect directly to battery
CL1.5_LDO_OUT A7 O PA LDO output
DIG_LDO_OUT A2, A3, B15, B26, B27, B35, B36 O Digital LDO output
QFN pin B26 or B27 must be shorted to other DIG_LDO_OUT pins on the PCB.
SRAM_LDO_OUT B1 O SRAM LDO output
DCO_LDO_OUT A12 O DCO LDO output
ADC_PPA_LDO_OUT A8 O ADC/PPA LDO output
VSS A24, A28 I Ground
VSS_DCO B11 I DCO ground
VSS_FREF B3 I Fast clock ground
(1) I = input; O = output; I/O = bidirectional
(2) I/O Type: Digital I/O cells. HY = input hysteresis, current = typical output current

4.2 Connections for Unused Signals

Table 4-2 lists the connections for unused signals.

Table 4-2 Connections for Unused Signals

FUNCTION PIN NUMBER DESCRIPTION
NC A1 Not connected
NC A10 Not connected
NC A11 Not connected
NC A14 Not connected
NC A18 Not connected
NC A19 Not connected
NC A20 Not connected
NC A21 Not connected
NC A22 Not connected
NC A23 Not connected
NC A27 Not connected
NC A30 Not connected
NC A31 Not connected
NC A40 Not connected
NC B9 Not connected
NC B10 Not connected
NC B16 Not connected
NC B17 Not connected
NC B20 Not connected
NC B23 Not connected
NC A13 TI internal use
NC A15 TI internal use
NC A16 TI internal use
NC A36 TI internal use
NC A37 TI internal use
NC A39 TI internal use
NC B12 TI internal use
NC B13 TI internal use
NC B14 TI internal use
NC B29 TI internal use
NC B30 TI internal use
NC B31 TI internal use
NC B28 TI internal use
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