SWRU553A September   2019  – February 2020 AWR1243 , AWR2243

 

  1.   AWRx Cascaded Radar RF Evaluation Module (MMWCAS-RF-EVM)
    1.     Trademarks
    2. 1 Getting Started
      1. 1.1 Introduction
      2. 1.2 EVM Revisions
      3. 1.3 Key Features
      4. 1.4 What is Included
        1. 1.4.1 Kit Hardware Contents
        2. 1.4.2 mmWave Studio and Matlab Post Processing
    3. 2 Hardware Description
      1. 2.1 Block Diagram
      2. 2.2 Attaching the MMWAVCAS-RF-EVM to the MMWAVCAS-DSP-EVM
      3. 2.3 Power Status LED Indicators
      4. 2.4 Reset LED Indicators
      5. 2.5 Connectors
        1. 2.5.1 Host Board Connectors(J4, J5)
        2. 2.5.2 Bench Power Connector(J6)
        3. 2.5.3 20 GHz LO Debug Connector (J3)
        4. 2.5.4 AWR OSC_CLKOUT Debug Header (J2)
        5. 2.5.5 AWR Debug Headers (J1_1, J1_2, J1_3, J1_4)
      6. 2.6 Antennas
        1. 2.6.1 TX and RX Antenna Arrays
        2. 2.6.2 PCB Antenna Element
          1. 2.6.2.1 RX Antenna Element Performance
          2. 2.6.2.2 TX Antenna Element Performance
        3. 2.6.3 Virtual Antenna Array
    4. 3 Design Files and Software Tools
      1. 3.1 Hardware Collateral
      2. 3.2 Software, Development Tools, and Example Codes for MMWCAS-RF-EVM
      3. 3.3 Critical AWRx Setup Notes
        1. 3.3.1 LDO Bypass Requirement
    5. 4 PCB Dimensions and Mounting Information
    6. 5 PCB Storage and Handling Recommendations
    7. 6 References
    8. 7 Regulatory Information
  2.   Revision History

2.5.1 Host Board Connectors(J4, J5)

The primary connector set on the MMWAVCAS-RF-EVM is the host board connector #1 (J4) and host board connector #2 (J5). These connectors are each implemeted with a Hirose FX23-120P-0.5SV15 Header. Connector #1 pinout containss all of the reset, boot, digital control and CSI2.0 data paths forAWRx #1 and AWRx #2. Connector #2 pinout contains the same for AWRx #3 and AWRx #4. Both connectors share a common 5.0 V power and GND return path. Primary power to the MMWCAS-RF-EVM is expected to be provided from a compatible host board through these connectors.

WARNING

It is required that any attached host board provide 5.0 V power conditioning. No 5.0 V power rail protection exists on the MMWAVCAS-RF-EVM design itself. The attached host board is expected to provide reverse polarity protectionand turn-on/off transient suppression. This is especially import to note when testing in an automotive alternator/battery powered system. The MMWAVCAS-DSP-EVM host board includes an automotive 12 V input supply rail for this purpose.

Figure 9. Host Board Connector #1 (J4), Schematic Excerpt
Figure 10. Host Board Connector #2 (J5), Schematic Excerpt

Table 2. Host Board Connector #1 (J4) Connector Definition

Pin Number Pin Name Pin Type (1) Pin Description
1 CONN_MONITOR_1 Passive Connection monitor - To be used with pin 120
2 AWR_1_MCU_CLKOUT_CONN Passive AWR #1 MCU_CLKOUT
3 GND Power System ground return
4 AWR_1_LVDS_VALID_P Output AWR #1 LVDS
5 AWR_1_LVDS_VALID_N Output AWR #1 LVDS
6 GND Power System ground return
7 GND Power System ground return
8 AWR_1_LVDS_FRCLK_P Output AWR #1 LVDS
9 AWR_1_LVDS_FRCLK_N Output AWR #1 LVDS
10 GND Power System ground return
11 GND Power System ground return
12 AWR_1_CSI2_TX3_P Output AWR #1 CSI2 TX3
13 AWR_1_CSI2_TX3_P Output AWR #1 CSI2 TX3
14 GND Power System ground return
15 GND Power System ground return
16 AWR_1_CSI2_TX2_P Output AWR #1 CSI2 TX2
17 AWR_1_CSI2_TX2_N Output AWR #1 CSI2 TX2
18 GND Power System ground return
19 AWR_1_CSI2_CLK_P Output AWR #1 CSI2 Clock
20 AWR_1_CSI2_CLK_N Output AWR #1 CSI2 Clock
21 GND Power System ground return
22 XWR_CONN_TP1 Passive Unused
23 GND Power System ground return
24 GND Power System ground return
25 AWR_1_CSI2_TX1_P Output AWR #1 CSI2 TX1
26 AWR_1_CSI2_TX1_N Output AWR #1 CSI2 TX1
27 GND Power System ground return
28 AWR_1_CSI2_TX0_P Output AWR #1 CSI2 TX0
29 AWR_1_CSI2_TX0_N Output AWR #1 CSI2 TX0
30 GND Power System ground return
31 GND Power System ground return
32 GND Power System ground return
33 AWR_2_LVDS_VALID_P Output AWR #2 LVDS
34 AWR_2_LVDS_VALID_N Output AWR #2 LVDS
35 GND Power System ground return
36 GND Power System ground return
37 AWR_2_LVDS_FRCLK_P Output AWR #2 LVDS
38 AWR_2_LVDS_FRCLK_N Output AWR #2 LVDS
39 GND Power System ground return
40 GND Power System ground return
41 AWR_2_CSI2_TX3_P Output AWR #2 CSI2 TX3
42 AWR_2_CSI2_TX3_N Output AWR #2 CSI2 TX3
43 GND Power System ground return
44 GND Power System ground return
45 AWR_2_CSI2_TX2_P Output AWR #2 CSI2 TX2
46 AWR_2_CSI2_TX2_N Output AWR #2 CSI2 TX2
47 GND Power System ground return
48 GND Power System ground return
49 AWR_2_CSI2_CLK_P Output AWR #2 CSI2 Clock
50 AWR_2_CSI2_CLK_N Output AWR #2 CSI2 Clock
51 GND Power System ground return
52 XWR_CONN_TP2 Passive Unused
53 GND Power System ground return
54 GND Power System ground return
55 AWR_2_CSI2_TX1_P Output AWR #2 CSI2 TX1
56 AWR_2_CSI2_TX1_N Output AWR #2 CSI2 TX1
57 GND Power System ground return
58 AWR_2_CSI2_TX0_P Output AWR #2 CSI2 TX0
59 AWR_2_CSI2_TX0_P Output AWR #2 CSI2 TX0
60 GND Power System ground return
61 AWR1_GPIO0 Bidirectional AWR #1 GPIO0
62 AWR1_GPIO1 Bidirectional AWR #1 GPIO1
63 AWR1_GPIO2 Bidirectional AWR #1 GPIO2
64 EXT_DIG_SYNC Input Alternative input to AWRx digital sync fanout buffer (U8)
65 GND Power System ground return
66 AWR_1_SPI_MISO1 Output AWR#1 SPI Slave MISO
67 AWR_1_SPI_HOST_INTR1 Output AWR#1 SPI Slave Interrupt
68 AWR_1_SPI_CS1 Input AWR#1 SPI Slave CS0N
69 AWR_1_SPI_MOSI1 Input AWR#1 SPI Slave MOSI
70 AWR_1_SPI_CLK1 Input AWR#1 SPI Slave SCLK
71 GND Power System ground return
72 PMIC1_SCL Input LP8752 4P (U3) PMIC I2C
73 PMIC1_SDA Bidirectional LP8752 4P (U3) PMIC I2C
74 EXT_40MHZ_CLK_1V8 Input Optional 40 MHz clock input for AWR #1 (U1_1) CLKP.
75 NERROR_OUT Input Open-Drain Logic OR ERROR_OUT from AWR#1, 2, 3 and 4
76 GND Power System ground return
77 AWR_1_UART_RX Input AWR#1 UART RX
78 AWR_1_UART_TX Output AWR#1 UART TX
79 AWR_1_MSS_LOGGER Output AWR #1 MSS debug log UART output
80 AWR_1_BSS_LOGGER Output AWR #1 MSS debug log UART output
81 GND Power System ground return
82 AWR_1_SOP2_PMICCLKOUT Input AWR#1 PMICCLKOUT/SOP2
83 AWR_1_SOP1_SYNCOUT Input AWR#1 SYNCOUT/SOP1 signal
84 AWR_1_SOP0_TDO Input AWR#1 TDO/SOP0 signal
85 AWR_1_NRST Input AWR#1 NRESET signal
86 AWR_1_WARM_RST Input AWR#1 WARM_RESET signal
87 GND Power System ground return
88 AWR_1_TCK Input AWR #1 JTAG
89 AWR_1_TMS Input AWR #1 JTAG
90 AWR_1_TDO Output AWR #1 JTAG
91 AWR_1_TDI Input AWR #1 JTAG
92 GND Power System ground return
93 AWR_2_SPI_MISO1 Output AWR#2 SPI Slave MISO
94 AWR_2_SPI_HOST_INTR1 Input AWR#2 SPI Slave Interrupt
95 GND Power System ground return
96 AWR_2_SPI_CS1 Input AWR#2 SPI Slave CS
97 AWR_2_SPI_MOSI1 Input AWR#2 SPI Slave MOSI
98 AWR_2_SPI_CLK1 Input AWR#2 SPI Slave SCLK
99 GND Power System ground return
100 AWR_2_UART_RX Output AWR#2 UART RX - TDA2x TX to AWR RX
101 AWR_2_UART_TX Input AWR#2 UART TX - AWR TX to TDA2x RX
102 AWR_2_MSS_LOGGER Output AWR #1 MSS debug log UART output
103 AWR_2_BSS_LOGGER Output AWR #1 BSS debug log UART output
104 GND Power System ground return
105 AWR_2_GPIO_0 Bidirectional AWR #1 GPIO0
106 AWR_2_GPIO_1 Bidirectional AWR #1 GPIO1
107 AWR_2_GPIO_2 Bidirectional AWR #1 GPIO2
108 GND Power System ground return
109 AWR_2_NRST Output AWR#2 NRESET signal
110 AWR_2_WARM_RST Output AWR#2 WARM_RESET signal
111 GND Power System ground return
112 AWR_2_SOP2_PMICCLKOUT Output AWR#2 PMICCLKOUT/SOP2
113 AWR_2_SOP1_SYNCOUT Output AWR#2 SYNCOUT/SOP1 signal
114 AWR_2_SOP0_TDO Output AWR#2 TDO/SOP0 signal
115 GND Power System ground return
116 AWR_2_TCK Input AWR #2 JTAG
117 AWR_2_TMS Input AWR #2 JTAG
118 AWR_2_TDO Output AWR #2 JTAG
119 AWR_2_TDI Input AWR #2 JTAG
120 CONN_MONITOR_1 Passive Connection monitor - To be used with pin 1
P1 GND Power Ground return
P2 GND Power Ground return
P3 EVM_5V0 Power System 5.0V power
P4 EVM_5V0 Power System 5.0V power
MH1 GND Power Plated mounting hole used for additional ground return
MH2 GND Power Plated mounting hole used for additional ground return
  1. Pin direction relative to the MMWAVCAS-RF-EVM. Output are signals generated by transmitters on the MMWCAS-RF-EVM. Inputs are signal intended for receivers on the MMWCAS-RF-EVM.

Table 3. Host Board Connector #2 (J5) Connector Definition

Pin Number Pin Name Pin Type Pin Description
1 CONN_MONITOR_2 Passive Connection monitor - To be used with pin 120
2 AWR_4_TDI Input AWR #4 JTAG
3 AWR_4_TDO Output AWR #4 JTAG
4 AWR_4_TMS Input AWR #4 JTAG
5 AWR_4_TCK Input AWR #4 JTAG
6 GND Power Ground return
7 AWR_4_SOP0_TDO Input AWR#4 TDO/SOP0
8 AWR_4_SOP1_SYNCOUT Input AWR#4 SYNCOUT/SOP1
9 AWR_4_SOP2_PMICCLKOUT Input AWR#4 PMICCLKOUT/SOP2
10 GND Power Ground return
11 AWR_4_WARM_RST Input AWR#4 WARM_RESET signal
12 AWR_4_NRST Input AWR#4 NRESET signal
13 GND Power Ground return
14 AWR_4_GPIO_2 Bidirectional AWR #4 GPIO2
15 AWR_4_GPIO_1 Bidirectional AWR #4 GPIO1
16 AWR_4_GPIO_0 Bidirectional AWR #4 GPIO0
17 GND Power Ground return
18 AWR_4_BSS_LOGGER Passive AWR #4 BSS debug log UART output
19 AWR_4_MSS_LOGGER Passive AWR #4 MSS debug log UART output
20 AWR_4_UART_TX Output AWR #4 UART TX
21 AWR_4_UART_RX Input AWR #4 UART RX
22 GND Power Ground return
23 AWR_4_SPI_CLK1 Output AWR #4 SPI CLK
24 AWR_4_SPI_MOSI1 Output AWR #4 SPI MOSI
25 AWR_4_SPI_CS1 Output AWR #4 SPI CS
26 GND Power Ground return
27 AWR_4_SPI_HOST_INTR1 Input AWR #4 SPI Host Interrupt
28 AWR_4_SPI_MISO1 Input AWR #4 SPI MISO
29 GND Power Ground return
30 AWR_3_TDI Input AWR #3 JTAG
31 AWR_3_TDO Output AWR #3 JTAG
32 AWR_3_TMS Input AWR #3 JTAG
33 AWR_3_TCK Input AWR #3 JTAG
34 GND Power Ground return
35 AWR_3_WARM_RST Input AWR#4 WARM_RESET signal
36 AWR_3_NRST Input AWR#4 NRESET signal
37 AWR_3_SOP0_TDO Input AWR #3 TDO/SOP0
38 AWR_3_SOP1_SYNCOUT Input AWR #3 SYNCOUT/SOP1
39 AWR_3_SOP2_PMICCLKOUT Input AWR #3 MICCLKOUT /SOP2
40 GND Power Ground return
41 AWR_3_BSS_LOGGER Passive AWR #3 BSS debug log UART output
42 AWR_3_MSS_LOGGER Passive AWR #3 MSS debug log UART output
43 AWR_3_UART_TX Input AWR #3 UART TX
44 AWR_3_UART_RX Output AWR #3 UART RX
45 GND Power Ground return
46 PMIC_BUCKEN_CONN PassInputive LP87524P (U3) and (U4) power enable input
47 PMIC_NRST_CONN Passive LP87524P (U3) and (U4) reset input
48 PMIC2_TMPSNS_SDA Bidirectional LP87524P (U4) and TMP112 (U9, U10) I2C
49 PMIC2_TMPSNS_SCL Input LP87524P (U4) and TMP112 (U9, U10) I2C
50 GND Power Ground return
51 AWR_3_SPI_CLK1 Input AWR #3 SPI CLK
52 AWR_3_SPI_MOSI1 Input AWR #3 SPI MOSI
53 AWR_3_SPI_CS1 Input AWR #3 SPI CS
54 AWR_3_SPI_HOST_INTR1 Output AWR #3 SPI Host Interupt
55 AWR_3_SPI_MISO1 Output AWR #3 SPI MISO
56 GND Power Ground return
57 TMPSNS_ALERT Output TMP112 (U9, U10) I2C temperature alert (3.3V open-drain)
58 AWR_3_GPIO_2 Bidirectional AWR #3 GPIO2
59 AWR_3_GPIO_1 Bidirectional AWR #3 GPIO1
60 AWR_3_GPIO_0 Bidirectional AWR #3 GPIO0
61 GND Power Ground return
62 AWR_4_CSI2_TX0_N Output AWR #4 CSI2 TX0
63 AWR_4_CSI2_TX0_P Output AWR #4 CSI2 TX0
64 GND Power Ground return
65 AWR_4_CSI2_TX1_N Output AWR #4 CSI2 TX1
66 AWR_4_CSI2_TX1_P Output AWR #4 CSI2 TX1
67 GND Power Ground return
68 GND Power Ground return
69 XWR_CONN_TP3 Passive Unused
70 GND Power Ground return
71 AWR_4_CSI2_CLK_N Output AWR #4 CSI2 Clock
72 AWR_4_CSI2_CLK_P Output AWR #4 CSI2 Clock
73 GND Power Ground return
74 GND Power Ground return
75 AWR_4_CSI2_TX2_N Output AWR #4 CSI2 TX2
76 AWR_4_CSI2_TX2_P Output AWR #4 CSI2 TX2
77 GND Power Ground return
78 GND Power Ground return
79 AWR_4_CSI2_TX3_P Output AWR #4 CSI2 TX3
80 AWR_4_CSI2_TX3_P Output AWR #4 CSI2 TX3
81 GND Power Ground return
82 GND Power Ground return
83 AWR_4_LVDS_FRCLK_N Output AWR #4 LVDS
84 AWR_4_LVDS_FRCLK_P Output AWR #4 LVDS
85 GND Power Ground return
86 GND Power Ground return
87 AWR_4_LVDS_VALID_N Output AWR #4 LVDS
88 AWR_4_LVDS_VALID_P Output AWR #4 LVDS
89 GND Power Ground return
90 GND Power Ground return
91 GND Power Ground return
92 AWR_3_CSI2_TX0_N Output AWR #3 CSI2 TX
93 AWR_3_CSI2_TX0_P Output AWR #3 CSI2 TX0
94 GND Power Ground return
95 AWR_3_CSI2_TX1_N Output AWR #3 CSI2 TX1
96 AWR_3_CSI2_TX1_P Output AWR #3 CSI2 TX1
97 GND Power Ground return
98 GND Power Ground return
99 XWR_CONN_TP4 Passive Unused
100 GND Power Ground return
101 AWR_3_CSI2_CLK_N Output AWR #3 CSI2 TX2
102 AWR_3_CSI2_CLK_P Output AWR #3 CSI2 TX2
103 GND Power Ground return
104 AWR_3_CSI2_TX2_N Input AWR #3 CSI2 TX2
105 AWR_3_CSI2_TX2_P Input AWR #3 CSI2 TX2
106 GND Power Ground return
107 GND Power Ground return
108 AWR_3_CSI2_TX3_N Input AWR #3 CSI2 TX3
109 AWR_3_CSI2_TX3_P Input AWR #3 CSI2 TX3
110 GND Power Ground return
111 GND Power Ground return
112 AWR_3_LVDS_FRCLK_N Passive AWR #3 LVDS
113 AWR_3_LVDS_FRCLK_P Passive AWR #3 LVDS
114 GND Power Ground return
115 GND Power Ground return
116 AWR_3_LVDS_VALID_N Passive AWR #3 LVDS
117 AWR_3_LVDS_VALID_P Passive AWR #3 LVDS
118 GND Power Ground return
119 SYSTEM_PGOOD Output System power good. Wired logic OR from LP87524P (U3, U4) PMIC.
120 CONN_MONITOR_2 Passive Connection monitor - To be used with pin 1
P1 SYSTEM_5V0 Power System 5.0V power
P2 SYSTEM_5V0 Power System 5.0V power
P3 GND Power Ground return
P4 GND Power Ground return
MH1 GND Power Ground return
MH2 GND Power Ground return
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