SWRZ073C May 2017 – May 2021 IWR1642
Partial Write After Full Data Width Write Fails to HS RAM, ADC Buffer and Data Transfer Memory if ECC is Enabled for that Memory
IWR1642 ES1.0
Partial data write after a full data width write would result in wrong data being written into HS RAM , ADC buffer and Data Transfer memory if ECC is enabled for that memory.
None. Silicon update will be provided by TI.