Revision(s) Affected:

IWR1642 ES1.0 and IWR1642 ES2.0

Description:

MSS Boot ROM Powers on DSP, Performs a Memory Initialisation of DSP L2 and downloads the program code to L2 memory. If the user application executes the STC or DSP power cycle, memory init is triggered again, hence erasing the L2 memory contents.

Workaround(s):

The workaround for Mem init would be to perform a Dummy mem init to reset a latch within the IP while keeping the destination domain in reset. This can be done by the application using the below sequence before running STC or DSP power cycling:

1. Set the GEM_CLK_EN_BYPASS_CTRL bit in the TOPRCM-> GEMPWRSMCFG2 register Bit 7 as ‘1’.
2. Set the GEM_GRSTN_GATE_BYPASS_CTRL bit in the TOPRCM-> GEMPWRSMCFG1 Bit 9 register as ‘1’.
3. Write a value of 0xFFFF in , DSS_REG ->L2MEMINITCFG1 register.
4. Write a value of 0xF in , DSS_REG ->L2MEMINITCFG2 register
5. Write a value of 0x0 in TOPRCM-> GEMPWRSMCFG1-> PWRSMOUTBYPCTRL register.