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SWRZ073C May 2017 – May 2021 IWR1642

1Introduction
2Device Nomenclature
3Device Markings
4Usage Notes
1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
5Advisory to Silicon Variant / Revision Map
6Known Design Exceptions to Functional Specifications
1. MSS#10
2. MSS#11
3. MSS#12
4. MSS#14
5. MSS#16
6. MSS#17
7. MSS#18
8. MSS#19
9. MSS#20
10. MSS#22
11. MSS#37B
12. MSS#38A
13. MSS#39
14. MSS#42
15. MSS#43A
16. MSS#44
17. MSS#45
18. ANA#06
19. ANA#08A
20. ANA#09A
21. ANA#10A
22. ANA#11A
23. ANA#12A
24. ANA#15
25. ANA#16
26. ANA#17A
27. ANA#18B
28. ANA#20
29. ANA#21A
30. ANA#22A
31. ANA#24A
32. ANA#27
33. DSS#01
34. DSS#02
35. DSS#03
36. DSS#04
37. DSS#05
38. DSS#06
39. DSS#07
7Trademarks
8Revision History

DSS#03

Different Number of Chirps in ADC Buffer's Ping and Pong Memory is not Supported

Revision(s) Affected:

IWR1642 ES1.0

Description:

Different number of chirps in ADC buffer's ping and pong memory is not supported. They need to be programmed to a same value and the configuration for number of chirps in Ping and Pong can only be changed at Sub-Frame boundary.

Workaround(s):

None. Silicon update will be provided by TI.