Revision(s) Affected:

IWR1443 ES1.0 and IWR1443 ES2.0

Description:

The activity on the CSI lines during the state transitions at the start and at the end of CSI transfer couples into the clock leading to glitches in the TX output.

Workaround(s):

Increase the idle time between chirps such that the "start of transfer" and "end of transfer" occur during the idle time between two chirps.

1. The IWR1443 eDMA sends data from ADCBuffer to High Speed Peripheral. At the start of each chirp, CSI-2 changes from Low Power Mode to Standard Mode output. At the completion of the chirp, CSI-2 goes back from Standard mode to Low Power Mode output. When CSI-2 changes mode, there is a clock contamination of the ADC subsystem. In order to not contaminate the measurement, the CSI-2 data Output must be finished before the end of the idle time chirp parameter.

   Bitrate_perChirp_perLane = (numRxch * DFEoutrate * (numDFEsamples/chirp) * (complexmode+1) *(numbits/sample[12,14,16]) / (numLanes)

   perChirp_Outperiod = Bitrate_perChirp_perLane / (DDC_Clkrate * 2)

   IdleTime = MAX(Synthesizer_IdleTime, perChirp_Outperiod)

   Note: Synthesizer_IdleTime can be calculated in the mmWave Sensing Estimator.

2. If the customer uses the LVDS High Speed output format, this ADC clock disturbance is not seen.