Revision(s) Affected:

IWR1443 ES1.0, IWR1443 ES2.0, and IWR1443 ES3.0

Description:

A spurious DMA request could be generated even when the SPI slave is not transferring data in the following condition sequence:

• The MIBSPI is configured in standard (non-multibuffered) SPI mode, as a slave
• The DMAREQEN bit (SPIINT0.16) is set to enable DMA requests
• The Chip Select (nSCS) pin is in an active state, but no transfers are active
• The SPI is disabled by clearing the SPIEN (SPIGCR1.24) bit from '1' to '0'

The above sequence triggers a false request pulse on the Receive DMA Request as soon as the SPIEN bit is cleared from '1' to '0'.

Workaround(s):

Whenever disabling the SPI, by clearing the SPIEN bit (SPIGCR1.24), first clear the DMAREQEN bit (SPIINT0.16) to '0', and then, clear the SPIEN bit.