Revision(s) Affected:

IWR1443 ES1.0, IWR1443 ES2.0, and IWR1443 ES3.0

Description:

The state of the MSS DMA is left pending and uncleared on any DMA MPU fault. The transfer that caused this MPU fault is left pending inside the DMA IP.

Any trigger on DMA REQ lines (could be caused by any module/IP that is hooked up to DMA in h/w) can re-trigger DMA to start executing the above pending transfer irrespective of whether that trigger is actually valid/enabled in DMA or that module/IP

Workaround(s):

For devices where the Boot ROM is executing the MSS DMA MPU Self tests. As part of application initialization, if the MSS DMA will be used, the following register field should be used to reset the MSS DMA IP so that the uncleared transfer is reset

1. Write MSS_RCM:SOFTRST1[31:24] 0xAD
2. Write MSS_RCM:SOFTRST1[31:24] 0x0

It is not recommended to use this configuration at any another instance other than that recommended here in this Errata.

On an actual Real time MPU Error, this error should be treated as a non-recoverable error and a warm reset should be issued to recover.