米6体育平台手机版

SWRZ074C May 2017 – May 2021 IWR1443

1Introduction
2Device Nomenclature
3Device Markings
4Usage Notes
1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
2. 4.2 Identification
5Advisory to Silicon Variant / Revision Map
6Known Design Exceptions to Functional Specifications
1. MSS#01
2. MSS#03A
3. MSS#04A
4. MSS#05A
5. MSS#06
6. MSS#07A
7. MSS#08
8. MSS#09
9. MSS#13
10. MSS#14
11. MSS#15
12. MSS#19
13. MSS#20
14. MSS#21A
15. MSS#22
16. MSS#23
17. MSS#24
18. MSS#25
19. MSS#26
20. MSS#27
21. MSS#28
22. MSS#29
23. MSS#30
24. MSS#31
25. MSS#32
26. MSS#33
27. MSS#35
28. MSS#37B
29. MSS#38A
30. MSS#39
31. MSS#40
32. MSS#43A
33. MSS#44
34. MSS#45
35. ANA#01
36. ANA#02
37. ANA#03
38. ANA#04
39. ANA#06
40. ANA#07
41. ANA#08A
42. ANA#10A
43. ANA#11A
44. ANA#12A
45. ANA#13B
46. ANA#15
47. ANA#16
48. ANA#17A
49. ANA#18B
50. ANA#20
51. ANA#21A
52. ANA#22A
53. ANA#24A
54. ANA#27
7Trademarks
8Revision History

MSS#31

CPU Abort Generated on a Write to Implemented CRC Space After a Write to Unimplemented CRC Space

Revision(s) Affected:

IWR1443 ES1.0, IWR1443 ES2.0, and IWR1443 ES3.0

Description:

An abort could be generated on a write to a legal address in the address offset region (0x0000–0x01FF) of the CRC register space when a normal mode write to an unimplemented address region (0x0200–0xFFFF) of the CRC register space is followed by a write to a legal address region (0x0000–0x01FF) of the CRC register space.

Workaround(s):

None.