SWRZ090C January   2020  – October 2023 AWR2243

 

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Advisory to Silicon Variant / Revision Map
  6. 5Known Design Exceptions to Functional Specifications
    1.     MSS#37
    2.     MSS#44A
    3. 5.1 MSS#50
    4. 5.2 MSS#51
    5.     ANA#08A
    6. 5.3 ANA#11A
    7. 5.4 ANA#12A
    8.     ANA#13B
    9.     ANA#18B
    10.     ANA#21A
    11.     ANA#22A
    12.     ANA#23
    13.     ANA#24
    14.     ANA#25
    15. 5.5 ANA#27A
    16.     ANA#28
    17.     ANA#53
  7.   Trademarks
  8.   Revision History

MSS#37

DCC Module Frequency Comparison can Report Erroneous Results

Revision(s) Affected:

AWR2243 ES1.0, ES1.1

Description:

The Dual-clock Comparator module, which is used to monitor a clock frequency while comparing with a known clock reference, could stop earlier than expected, and, thus, indicating the measured clock frequency to be lower. This is due to a clock domain crossing issue causing the error detection logic to get triggered. This incorrect reporting, can cause a rare failure in the DCC monitor used to monitor internal clock frequencies.

Workaround(s):

Multiple measurements can be taken for the same clock pairs, and the median of the frequencies reported can be used for detecting failure.