米6体育平台手机版

SWRZ097D April 2020 – November 2022 AWR6843

1Introduction
2Device Nomenclature
3Device Markings
4Usage Notes
1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
5Advisory to Silicon Variant / Revision Map
6Known Design Exceptions to Functional Specifications
1. MSS#25
2. MSS#26
3. MSS#27
4. MSS#28
5. MSS#29
6. MSS#30
7. MSS#31
8. MSS#32
9. MSS#33
10. MSS#34
11. MSS#36
12. MSS#37B
13. MSS#38A
14. MSS#39
15. MSS#40
16. MSS#41
17. MSS#42A
18. MSS#43A
19. MSS#44A
20. MSS#45
21. 6.1 MSS#50
22. 6.2 MSS#51
23. ANA#11B
24. 6.3 ANA#12A
25. ANA#13B
26. ANA#14
27. ANA#15
28. ANA#16
29. ANA#17A
30. ANA#18B
31. ANA#19
32. ANA#20
33. ANA#21
34. ANA#22A
35. ANA#27A
7Trademarks
1. Revision History

MSS#31

CPU Abort Generated on a Write to Implemented CRC Space After a Write to Unimplemented CRC Space

Revision(s) Affected:

AWR6843 ES2.0

Description:

An abort could be generated on a write to a legal address in the address offset region (0x0000–0x01FF) of the CRC register space when a normal mode write to an unimplemented address region (0x0200–0xFFFF) of the CRC register space is followed by a write to a legal address region (0x0000–0x01FF) of the CRC register space.

Workaround(s):

None.