SWRZ101B December 2021 – December 2023 AM2732 , AM2732-Q1
DSP PBIST Reset changing DSP L2 clock
During self-test operation of DSS subsystem by DSP, L2 memories are in functional mode and clock should not be disturbed. PBIST_ST_KEY register has to be set to access PBIST controller. MMR registers are for configuration of memory self-test and control for the select line of the clock mux added on L2 clock path.
Configuring the register will create the glitch at the L2 clock mux as it dynamically switches the select line while both clocks are active.
DSP PBIST is done by MSS.