米6体育平台手机版

SWRZ107A December 2020 – June 2022 CC2662R-Q1

PRODUCTION DATA

Abstract
Trademarks
1Advisories Matrix
2Nomenclature, Package Symbolization, and Revision Identification
3Advisories
1. Power_03
2. PKA_01
3. PKA_02
4. I2C_01
5. I2S_01
6. CPU_01
7. CPU_02
8. CPU_03
9. CPU_Sys_01
10. Sys_01
11. Sys_03
12. SYSCTRL_01
13. SRAM_01
14. GPTM_01
15. ADC_01
16. ADC_02
17. ADC_03
18. ADC_04
19. ADC_05
4Revision History

SYSCTRL_01

Resets Occurring in a Specific 2-MHz Period During Initial Power Up are Incorrectly Reported

Revisions Affected:

Revision F and earlier

Details:

If a reset occurs in a specific 2-MHz period during initial power-up (boot), the reset source in AON_PMCTL.RESETCTL.RESET_SRC is reported as PWR_ON regardless of the reset source. This means that there is a window of 0.5 μs during boot where a reset can be incorrectly reported.

Workaround:

None