米6体育平台手机版

SWRZ115B March 2021 – May 2024 AWR1843AOP

1
1Introduction
2Device Nomenclature
3Device Markings
4Usage Notes
1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
5Advisory to Silicon Variant / Revision Map
6Known Design Exceptions to Functional Specifications
1. MSS#03
2. MSS#04A
3. MSS#05A
4. MSS#13
5. MSS#17
6. MSS#18
7. MSS#19
8. MSS#20
9. MSS#21A
10. MSS#22
11. MSS#23
12. MSS#24
13. MSS#25
14. MSS#26
15. MSS#27
16. MSS#28
17. MSS#29
18. MSS#30
19. MSS#31
20. MSS#32
21. MSS#33
22. MSS#34
23. MSS#35
24. MSS#37B
25. MSS#38A
26. MSS#39
27. MSS#40
28. MSS#42
29. MSS#43A
30. MSS#44
31. MSS#45
32. ANA#08A
33. ANA#09A
34. ANA#10
35. ANA#11A
36. ANA#12A
37. ANA#13B
38. ANA#15
39. ANA#16
40. ANA#17A
41. ANA#18B
42. ANA#20
43. ANA#21B
44. ANA#22A
45. ANA#24A
46. ANA#27
47. PACKAGE#02A
7Trademarks
8Revision History

MSS#31

CPU Abort Generated on a Write to Implemented CRC Space After a Write to Unimplemented CRC Space

Revision(s) Affected:

AWR1843AOP ES1.0

Description:

An abort could be generated on a write to a legal address in the address offset region (0x0000–0x01FF) of the CRC register space when a normal mode write to an unimplemented address region (0x0200–0xFFFF) of the CRC register space is followed by a write to a legal address region (0x0000–0x01FF) of the CRC register space.

Workaround(s):

None.