Revision(s) Affected:

AWR1843AOP ES1.0

Description:

The MibSPI module, when configured in multibuffered peripheral mode with 3-functional pins (CLK, SIMO, SOMI) or 4-functional pins (CLK, SIMO, SOMI, nENA), could transmit incorrect data when all the following conditions are met:

• MibSPI module is configured in multibuffered mode,
• Module is configured to be a peripheral in the SPI communication,
• SPI communication is configured to be in 3-pin mode or 4-pin mode with nENA,
• Clock phase for SPICLK is 1, and
• SPICLK frequency is MSS_VCLK frequency / 12 or slower

Workaround(s):

The issue can be avoided by setting the CSHOLD bit in the control field of the TX RAM (Multi-Buffer RAM Transmit Data Register). The nCS is not used as a functional signal in this communication; hence, setting the CSHOLD bit does not cause any other effect on the SPI communication.