Revision(s) Affected:

AWR1843AOP ES1.0

Description:

Rare occurrences of failures have been observed in the Dual-Clock Comparator (DCC) module, as a result the APLL or Synthesizer may report a failure.

Workaround(s):

Workaround #1:

Any APLL calibration failure needs to be responded with a reset cycle.

or

Workaround #2:

Any SYNTH calibration failure reported by the BSS will require an RFinit.