米6体育平台手机版

SWRZ127A February 2022 – June 2022 CC2651R3SIPA

PRODUCTION DATA

Abstract
Trademarks
1Advisories Matrix
2Nomenclature, Package Symbolization, and Revision Identification
3Advisories
1. Radio_04
2. Power_03
3. I2C_01
4. I2S_01
5. CPU_01
6. CPU_02
7. CPU_Sys_01
8. Sys_01
9. 3.1 Sys_05
10. SYSCTRL_01
11. ADC_01
12. ADC_02
13. ADC_03
4Revision History

CPU_Sys_01

The SysTick Calibration Value (Register Field CPU_SCS.STCR.TENMS) Used to Set Up 10-ms Periodic Ticks is Incorrect When the System CPU is Running Off Divided Down 48-MHz Clock

Revisions Affected:

Revision B

Details:

When using the Arm^® Cortex^® SysTick timer, the TENMS register field (CPU_SCS.STCR.TENMS) will always shows the value corresponding to a 48-MHz CPU clock, regardless of the CPU division factor.

Workarounds:

One of the following two workarounds must be implemented:

Workaround 1: Do not use a divided down system CPU clock. In general, power savings are maximized by completing a task at full clock speed and then stopping the system CPU entirely after the task is complete.

Workaround 2: Read the system CPU division factor from the PRCM.CPUCLKDIV.RATIO register and compensate the TENMS field in software based on this value.

TI-provided drivers do not offer any functionality to divide the system CPU clock.