SWRZ127A February 2022 – June 2022 CC2651R3SIPA
PRODUCTION DATA
I2C Module Controller Status Bit is Set Late
Revision B
The I2C.MSTAT[0] bit is not set immediately after writing to the I2C.MCTRL register. This can lead an I2C controller to believe it is no longer busy and continuing to write data.
Add four NOPs between writing to the MCTRL register and polling the MSTAT register.
The workaround is implemented in the TI-provided I2C Controller driver (I2CCC26XX.c) and in the I2C driver Library APIs (driverlib/i2c.c).
The workaround is available in all Software Development Kit (SDK) versions.