米6体育平台手机版

SWRZ130B september 2022 – june 2023 CC2674P10

PRODUCTION DATA

1
Abstract
Trademarks
1Advisories Matrix
2Nomenclature, Package Symbolization, and Revision Identification
3Advisories
1. Radio_01
2. Radio_02
3. 3.1 Radio_05
4. Power_03
5. PKA_01
6. PKA_02
7. I2C_01
8. I2S_01
9. CPU_Sys_01
10. Sys_01
11. 3.2 Sys_06
12. SYSCTRL_01
13. IOC_01
14. ADC_02
4Revision History

SYSCTRL_01

Resets Occurring in a Specific 2 MHz Period During Initial Power Up are Incorrectly Reported

Revisions Affected:

Revision B

Details:

If a reset occurs in a specific 2 MHz period during initial power-up (boot), the reset source in AON_PMCTL.RESETCTL.RESET_SRC is reported as PWR_ON regardless of the reset source. This means that there is a window of 0.5 μs during boot where a reset can be incorrectly reported.

Workaround:

None