Hang scenario with SPI waiting for CPU intervention forever.
Revisions Affected
A
Details
When the CPU is reading or writing the SPI FIFO using FIFO level
triggers to generate interrupts, the system can hang. After the first interrupt is
serviced, the FIFO level can permanently be below or above the configured threshold
and not generate a subsequent CPU interrupt. This can lead to a hang scenario with
SPI waiting for CPU intervention forever.
Workaround
- Use polling of FIFO status within
SPI and do
not
rely on FIFO level configured interrupts, or
- Use only empty/overflow
interrupts and don't use FIFO level configured interrupts, or
- Use FIFO level configured
interrupts along with empty (for TXFIFO) and overflow (for RXFIFO) as a failsafe
to avoid hang scenarios.