Revision(s) Affected

AWRL1432ES1.1, ES2.0

Details

Smart-idle mode needs to be disabled for SPI before the first trigger for data transfer access. If the SPI smart-idle mode is required to be enabled, it has to be enabled again once the access is complete.

Workaround

It is recommended to follow the below sequence:

Auto Wake-up = 1 & Controller mode

1. Configure McSPI as required
2. Enable SmartIdle (by setting LPRADAR:APP_CTRL:SPI1_SMART_IDLE_ENABLE for SPI1 and LPRADAR:APP_CTRL:SPI2_SMART_IDLE_ENABLE for SPI 2 )after ensuring that there is no pending transaction from/to SPI or any more access to be done to McSPI by CPU or DMA
3. If any register or memory access to McSPI has to be done, disable SmartIDLE mode (by setting LPRADAR:APP_CTRL:SPI1_SMART_IDLE_ENABLE=0 for SPI 1 and LPRADAR:APP_CTRL:SPI2_SMART_IDLE_ENABLE =0 for SPI 2)
4. In Controller mode, the external host is not going to toggle the SPI_CS, hence there will not be any wakeup => there is no difference between (LPRADAR:APP_CTRL:SPI1_SMART_IDLE_AUTO_EN is 1 or 0 for SPI 1 and LPRADAR:APP_CTRL:SPI2_SMART_IDLE_AUTO_EN is 1 or 0 )

Auto Wake-up = 1 & Peripheral mode

1. Configure McSPI as required

2. Enable SmartIdle (by setting LPRADAR:APP_CTRL:SPI1_SMART_IDLE_ENABLE for SPI1 and LPRADAR:APP_CTRL:SPI2_SMART_IDLE_ENABLE for SPI 2 ) after ensuring that there is no pending transaction from/to SPI or any more access to be done to McSPI by CPU or DMA
3. If any register or memory access to McSPI has to be done by any master (DMA / CPU), disable SmartIDLE mode (by setting LPRADAR:APP_CTRL:SPI1_SMART_IDLE_ENABLE=0 for SPI 1 and LPRADAR:APP_CTRL:SPI2_SMART_IDLE_ENABLE =0 for SPI 2)
4. If there is wakeup from McSPI (because of some SPI_CS toggle), then the clock is automatically enabled.
5. Disable SmartIdle configuration (by setting LPRADAR:APP_CTRL:SPI1_SMART_IDLE_ENABLE=0 for SPI 1 and LPRADAR:APP_CTRL:SPI2_SMART_IDLE_ENABLE =0 for SPI 2 ) to do the register access.

The below table shows the Register Addresses for above workaround.