SWRZ149A July 2023 – August 2024 IWRL1432
PRODUCTION DATA
5.13 DIG #14
Corrupted Data Store for Partial Write in Shared Memory
Revision(s) Affected
IWRL1432 ES1.1, ES2.0
Details
Internal shared memory has ODD and EVEN banking structure. For a particular address range, partial write (less than 32 bit) to EVEN bank corrupts same address of ODD bank with next data on the bus. When shared memory is allocated to M4/M3, back to back full word write access to location A followed by sub-word write access to location B corrupts data in location A.
When memory is shared with M4/M3, issue is seen in the following address range:
| Memory | Address Range |
|---|---|
| APP_CPU_SHARED_RAM | 0x0048 0000 - 0x004B FFFC |
| FEC_CPU_SHARED_RAM | 0x2120 8000 - 0x2121 FFFC |
Figure 5-1 Shared Memory Logic Diagram
When Shared with M4/M3 When shared with M3/M4, the incoming data bit width is 32 bit as shown in the diagram. So, depending on LSB of address, signals are sent to either left or right ECC wrapper.
Workaround
- Use shared memories as code memory when shared with processor.
- Disable ECC for non functional safety devices – ECC is disabled for shared memories in RBL for non functional safety devices.