米6体育平台手机版

SWRZ153 November 2023 CC1312PSIP

1
Abstract
1Advisories Matrix
2Nomenclature, Package Symbolization, and Revision Identification
3Advisories
1. Advisory Power_03
2. Advisory PKA_01
3. Advisory PKA_02
4. Advisory I2C_01
5. Advisory I2S_01
6. Advisory CPU_01
7. Advisory CPU_02
8. Advisory CPU_03
9. Advisory CPU_Sys_01
10. Advisory Sys_01
11. 3.1 Sys_05
12. Advisory SYSCTRL_01
13. IOC_01
14. SRAM_01
15. GPTM_01
16. ADC_01
17. ADC_02
18. ADC_03
19. ADC_04
20. ADC_05
Trademarks
4Revision History

Advisory CPU_Sys_01

The SysTick Calibration Value (Register Field CPU_SCS.STCR.TENMS) Used to Set Up 10-ms Periodic Ticks is Incorrect When the System CPU is Running Off Divided Down 48-MHz Clock

Revisions Affected:

Revision F

Details:

When using the Arm^® Cortex^® SysTick timer, the TENMS register field (CPU_SCS.STCR.TENMS) will always shows the value corresponding to a 48-MHz CPU clock, regardless of the CPU division factor.

Workarounds:

One of the following two workarounds must be implemented:

Workaround 1: Do not use a divided down system CPU clock. In general, power savings are maximized by completing a task at full clock speed and then stopping the system CPU entirely after the task is complete.

Workaround 2: Read the system CPU division factor from the PRCM.CPUCLKDIV.RATIO register and compensate the TENMS field in software based on this value.

TI-provided drivers do not offer any functionality to divide the system CPU clock.