The following figures show the FET switch node voltage (YELLOW) at TP7 under various input and output conditions.

Figure 4-3 V_IN = 420 V and V_OUT = 350 V at 2 A.
Resistive Load (V_OUT: 250 V/DIV, 2 µs/DIV, BWL = 800 MHz)

Figure 4-4 V_IN = 420 V and V_OUT = 400 V at 2 A.
Resistive Load (V_OUT: 250 V/DIV, 2 µs/DIV, BWL = 800 MHz)

Figure 4-5 V_IN = 400 V and V_OUT = 400 V at 2 A.
Resistive Load (V_OUT: 250 V/DIV, 2 µs/DIV, BWL = 800 MHz)

Figure 4-6 V_IN = 400 V and V_OUT = 400 V at 70 mA.
Resistive Load (V_OUT: 250 V/DIV, 2 µs/DIV, BWL = 800 MHz)

Figure 4-7 V_IN = 340 V and V_OUT = 400 V at 2 A.
Resistive Load (V_OUT: 250 V/DIV, 2 µs/DIV, BWL = 800 MHz)

The following figure shows the FET switch node rise time of 22.8 ns at TP7.

Figure 4-8 V_IN = 400 V and V_OUT = 400 V at 2 A.
Resistive Load (V_OUT: 250 V/DIV, 40 ns/DIV, BWL = 800 MHz)