TIDT328 april 2023
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10 V / div 2 ms / div full bandwidth |
Modulation set to 120 Hz, sinusoidal output voltage looks promising, but the output ripple voltage is increased by lowering output impedance.
Ripple reduction – instead of using a single output capacitor 2.2 µF,100 V, X7R, 1210, a small improvement can be achieved by using several smaller capacitors in parallel ⇒ 3 × 1 µF, 100 V, X7R, 1206, that is, Murata GCJ31CR72A105KA01.