TIDT412A October   2024  – November 2024

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5. 1Test Prerequisites
    1. 1.1 Voltage and Current Requirements
    2. 1.2 Required Equipment
    3. 1.3 Considerations
    4. 1.4 Dimensions
  6. 2Testing and Results
    1. 2.1 Efficiency Graphs
    2. 2.2 Efficiency Data
    3. 2.3 Thermal Images
    4. 2.4 Bode Plots
    5. 2.5 PWM Duty Cycle Versus Output Voltage
  7. 3Waveforms
    1. 3.1 Switching
    2. 3.2 Output Voltage Transitions
    3. 3.3 Load Transients
    4. 3.4 High Current Load Transients
    5. 3.5 Start-up and Shutdown Sequences
    6. 3.6 Overvoltage Protection
    7. 3.7 Reverse Voltage Protection

Switching

Figure 3-1 and Figure 3-2 show the switching waveforms across different output voltages, but all use an input voltage of 48V, and a resistive load of 2.5Ω. These signals were measured at the source pins of the high-side power stage FETs (Q5 and Q6) but only one waveform is shown, as operation is similar across the FETs. Additionally, a tip and barrel probe was used for this measurement, with the tip at the source pins of the FET and the barrel at the GND of the nearby input capacitors.

Figure 3-1 was taken with an output voltage of 6V and has an overshoot of 3.2V above the 48V input voltage, while Figure 3-2 with an output voltage of 20V has an overshoot of 2.8V above of the 48V input voltage. This is well within the 60V drain-to-source voltage rating of the FET.

PMP23468 6VOUT Switching
          Waveform Figure 3-1 6VOUT Switching Waveform
PMP23468 20VOUT Switching
          Waveform Figure 3-2 20VOUT Switching Waveform