7.7 Clock Generation (PWM)

Connecting TRIG to THRES, as Figure 17 shows, causes the timer to run as a multivibrator. The capacitor C1 charges through R1 and D1 to the threshold voltage level (approximately 0.67 V_DD) and then discharges through R2 only to the value of the trigger voltage level (approximately 0.33 V_DD). As Figure 18 shows, the output is high during the charging cycle (t_c(H)) and low during the discharge cycle (t_c(L)).

Figure 17. TLC555-Q1 Clock Generation

Figure 18. Trigger and Threshold Voltage Waveform

The values of R1, D1, R2, and C1 control the duty cycle, as the following equations show:

Equation 16.

• t_c(H) = 100 nF × 10 kΩ × ln 2 = 693 µs
• t_c(L) = 100 nF × 39 kΩ × ln 2 = 2.7 ms
• Period = t_c(H) + t_c(L) = 3.39 ms
• Output waveform duty cycle = 20.4%

The preceding formulas do not allow for any propagation delay times from the TRIG and THRES inputs to DISCH. These delay times add directly to the period and create differences between calculated and actual values that increase with frequency. In addition, the internal ON-state resistance (r_ON) during discharge adds to R2 to provide another source of timing error in the calculation when R2 is very low or r_ON is very high. These errors can be canceled out by applying a feedback loop.