This design provides an efficient power tree architecture, as shown in Figure 2-9. The input voltage rail of 5 V is configured as the power supply for each part; power-up sequence and power-down sequence are divided into 5 orders, as shown in Section 2.2.2. The power sequence controller is achieved by a sequencer and a supervisor. The sequence order of VDD_MPU and VDD_CORE is achieved by leveraging the 3.3-V converter's power good signal.

Figure 2-9 Power Sequencing Platform Diagram