3.4.6 System Clock Synchronization

The schematic shown in Figure 11 can be synchronized to an external clock signal only if the duty cycle of the latter is larger than the duty cycle of the controller itself (larger than 93%). This design can be synchronized to an external clock with 50% Duty cycle by implementing the solution shown in Figure 17. The various point of load supplies can be synchronized to external clock which is available on the power connector discussed in section Power and data output connector. The signal from clock source pin DC_DC_CLK_1 is further is divided and distributed to respective supplies supplies and their switching frequencies. Figure 17 shows schematic of the implementation. The source clock is first buffered through LMV112SD and then one output is fed to -5.3V rail at 1 MHz (SYNC -5V_TX) and another one is given as an input to 9Ch-integrated clock buffer and divider device CDCE949. The 8 outputs are 500kHz for the seven TPS54218 buck devices and one TPS61178 for 5V rail, the 9th output is 250kHz for the HV circuit. The configuration of the device CDCE949 can be stored in the integrated EEPROM CDCEL9XXPROGEVM or over I2C. If CDCEL9XXPROGEVM is used, the configuration file can be found in the design files.

Figure 17. Schematic of External Clock Synchronization Implementation

The high voltage circuit can be synchronized to an external clock with 50% duty cycle. The controller LM3488 imposes a limit on the duty cycle clock pulse width to be larger than the duty cycle of the supply which is very high in the current implementation. The schematic shown in Figure 17 depicts the implementation. Two diodes forming an OR-ing system are introduced. One diode is placed from the gate drive pin to the sync pin. The other one comes from the input clock signal. The resistor R36 and R39 are series SYNC resistor and discharge resistor, respectively. If DR_pin is more positive than SYNC_HV_TX, then D1 will be reverse-biased and the SYNC-PIN will be driven high from D2. If DR_pin is less positive than SYNC_HV_TX, then D2 will be reverse-biased and SYNC_PIN will be driven High from D1. Test results are shown in Figure 18 and Figure 19 at the case of no load and full load.

Figure 18. Synchronization at No Load With 50% Duty Cycle Clock

Figure 19. Synchronization at Full Load With 50% Duty Cycle Clock