5.2 USB Section Layout Guidelines

The USB data section comprises of HD3SS3220 Mux controller and FX3 data serializer. Figure 53 shows the routing and placement of the various high speed sections. The device HD3SS3220 has high speed differential signals SSTX and SSRX. The length mismatch should be minimal between these two pair. The design keeps < 3mil length mismatch between these two pair. Figure 53 also shows various other sections of the circuit such as low voltage circuit with the EMI shield placed with all the clocking and LV inductor placed inside. This side faces the TX+RX AFE board hence in order to reduce the EMI noise coupling, a shield is placed between the two. The top most part is a plane comprising the ground of the high voltage circuit. There is no component placed in this region to keep space for the transducer connector and transducer and also to keep a shielding layer from the bottom side.

Figure 53. Placement and Layout of the Different Sections of the Design, High Speed Data Section, LV and HV Section (top layer)

Figure 54 shows the corresponding bottom side of the board highlighting various sections of the board. On this side, at the top, complete high voltage circuit is placed and its layout is discussed separately in Section 5.2.

Figure 54. Placement and Layout of the Different Sections of the Design, High-speed Data Section, LV and HV Section (bottom layer)

Figure 55 shows the placement and layout of the high-speed 32-bit data signals routed on signal layers. The maximum length of the routed signals is kept 1500 mil with length mismatch of < 100mil. The impedance of the layer is 90 ohm.

Figure 55. Placement and Layout of the High-Speed 32-Bit Data Signals Routed on Signal Layers (highlighted yellow area shows routing)