This reference design implements a 4-switch buck-boost topology to step up or step down the panel current to string current, so this reference design can be used in many applications that need to operate module-level optimization.

This topology can also be configured to a buck topology by using a bypass resistor to bypass the upper switch of the boost side. This bypass resistor simplifies the design and implementation of both topologies.

Figure 3-6 Configurable Four-Switch Buck-Boost Topology

A stack-carrier modulation is used to generate the PWMs for the 4-switch buck-boost topology, as shown in Figure 3-6.

The carrier of the buck stage and boost stage is stacked. The buck carrier amplitude is between 0 to 1.05, the boost carrier amplitude is between 0.95 to 2, so, naturally, these two carriers have an overlapping when the modulator is between 0.95 to 1.05. Thus, this modulation scheme can seamlessly change from buck mode to buck-boost mode and boost mode, as shown in Figure 3-7.

Figure 3-7 Four Switch Buck-Boost Topology Modulation Scheme

Adjusting the carrier starting point in C2000 causes a loss of PWM resolution, if using the theoretical implementation, then the PWM resolution can lose almost 50%, this reduces the performance of the converter. So in software, this is realized by adjusting the modulator of the boost stage and buck stage, as shown in Figure 3-8, the carrier of boost and buck is still between 0–1, while the modulator is between 0–2. By simply multiplying the modulator of buck by 0.95, which is equivalent to multiplying the carrier of buck by 1.05. The boost stage is similar; first, subtract the modulator of boost by 0.95, and then, multiply the result by 0.95 to get the final modulator of the boost stage. In Equation 1 and Equation 2, M_buck is the modulator of the buck stage, M_boost is the modulator of the boost stage:

Figure 3-8 Four Switch Buck-Boost Topology Modulation Scheme Implemented in C2000™

To make this four-switch buck-boost power stage more compact and efficient, the LMG2100R026 half-bridge power stage is selected for this reference design for the high maximum V_DS of 93V continuous, 100V pulsed rating, and low Q_g and R_DS(on) of 12nC and 2.6mΩ, respectively, at a gate voltage of 5V. Also, the 7.0mm × 4.5mm × 0.89mm lead-free package saves a lot of PCB area, and this package is optimized for a smaller high-frequency current loop to provide the very small ringing during the switching period. This is a desirable design for a compact, high power density, and high-efficiency power optimizer of the medium power rating.