ZHCABE7A November 2021 – April 2022 PCM5120-Q1 , PCM6120-Q1 , TLV320ADC5120 , TLV320ADC6120
DRE 默认参数对大多数应用都很有效。默认的 DRE 触发阈值为 -54dB。这为 DRE 提供了足够的余量以便对突然出现的强烈信号及时做出反应。增大 DRE 触发阈值可提高小信号性能，但会减小切换到起音周期之前的可用余量。可以通过减小起音时间来缓解该问题。本节展示了一个示例，其中设置了更高的 DRE 触发阈值并调整了时间常数以使 DRE 响应更快。
# Key: w 9C XX YY ==> write to I2C address 0x9c, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device.Note that there are
# other valid sequences depending on which features are used.
#
# See the corresponding EVM user guide for jumper settings and audio connections.
#
# Differential 2-channel : INP1/INM1 - Ch1, INP2/INM2 - Ch2
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 11.2896 MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD and AVDD power supplies
# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.
# Wait for 1ms.
#
w 9C 00 00 # Goto Page 0
w 9C 02 81 # Exit Sleep mode
d 10 # Wait for 16 ms
w 9C 01 01 # Reset
w 9C 6C 44 # Enable DRE in DSP_CFG1 and Override DRE parameters with user values
w 9C 3C 01 # Select DRE on Ch. 1 using CH1_CFG0
w 9C 41 01 # Select DRE on Ch. 2 using CH2_CFG0
w 9C 6D 4B # DRE LVL = -36 dB, DRE GAIN = 24 dB
w 9C 00 05 # Goto Page 5
w 9C 7C 7F B5 16 50 # DRE Release Time Alpha
w 9C 00 05 # Goto Page 6
w 9C 08 00 4A E9 B0 # DRE Release Time Beta
w 9C 0C 01 50 DB 39 # DRE Attack Time Alpha
w 9C 10 7E B5 16 50 # DRE Attack Time Beta
w 9C 18 00 00 02 00 # DRE Attack Debounce
w 9C 1C 00 04 B0 00 # DRE Release Debounce
w 9C 3C 00 00 01 00 # DRE Attack Hysteresis
w 9C 34 00 00 03 00 # DRE Release Hysteresis
w 9C 00 00 # Goto Page 0
w 9C 07 30 # TDM Mode with 32 Bits/Channel
w 9C 73 c0 # Enable Ch.1 - Ch.2
w 9C 74 f0 # Enable ASI Output channels
w 9C 75 e0 # Power up ADC
要启用 DRC 算法而不是具有与上述示例相同的参数集的 DRE 算法，请将 DSP_CFG1（Page 0，寄存器 0x6c）设置为值 0x46（而不是 DRE 的 0x44）。