ZHCADU5 February 2024 MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1
volatile bool gCheckADC;
/* Filtered Result */
uint32_t gResult = 0;
/* ADC Value Output */
uint32_t gADCResult = 0;
/* Scaling Factor, Q8 value (0-255) */
uint32_t gBeta = 16;
const DL_MathACL_operationConfig gMpyConfig = {
.opType = DL_MATHACL_OP_TYPE_MAC,
.opSign = DL_MATHACL_OPSIGN_SIGNED,
.iterations = 0,
.scaleFactor = 0,
.qType = DL_MATHACL_Q_TYPE_Q8};
int main(void)
{
SYSCFG_DL_init();
NVIC_EnableIRQ(ADC12_0_INST_INT_IRQN);
gCheckADC = false;
DL_ADC12_startConversion(ADC12_0_INST);
/* Configure MathACL for Multiply and Accumulate */
DL_MathACL_configOperation(MATHACL, &gMpyConfig, 0, 0 );
DL_MathACL_enableSaturation(MATHACL);
while (1) {
while (false == gCheckADC) {
__WFE();
}
gCheckADC = false;
/* Calculate IIR Filter Output */
gADCResult = DL_ADC12_getMemResult(ADC12_0_INST, DL_ADC12_MEM_IDX_0);
/* Set Operand One last */
DL_MathACL_setOperandTwo(MATHACL, gADCResult - gResult);
DL_MathACL_setOperandOne(MATHACL, gBeta);
DL_MathACL_waitForOperation(MATHACL);
gResult = DL_MathACL_getResultOne(MATHACL);
DL_DAC12_output12(DAC0, gResult);
}
}
/* Set the ADC Result flag to trigger our main loop to process the new data */
void ADC12_0_INST_IRQHandler(void)
{
switch (DL_ADC12_getPendingInterrupt(ADC12_0_INST)) {
case DL_ADC12_IIDX_MEM0_RESULT_LOADED:
gCheckADC = true;
break;
default:
break;
}
}