ZHCAEC8 August 2024 TAC5111-Q1 , TAC5212-Q1 , TAC5311-Q1 , TAC5312-Q1 , TAC5411-Q1 , TAC5412-Q1 , TAD5212-Q1

6 示例

表 6-1 提供了一个与 TAx5xxx-Q1 器件兼容且带有以下参数的示例脚本。

表 6-1 带有参数的示例脚本

失真限制器	欠压保护器	热折返
启动系数：-0.2dB/步释放系数：0.5dB/步保持计数器：1ms 拐点：11V 最大阈值：-2dB 最小阈值：-40dB 斜率：1V/V	启动系数：-0.5dB/步释放系数：0.1dB/步保持计数器：2ms 临界电平 1：11V 临界电平 2：3V 增益级别 1：-3dB 增益级别 2：-20dB	启动系数：-0.5dB/步释放系数：0.1dB/步保持计数器：2ms 温度阈值： 20°C 最大衰减：-30dB 斜率：-1V/V

# Key: w a0 XX YY ==> write to I2C address 0xa0, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
# See the corresponding EVM user guide for jumper settings and audio connections.
#
# Line-Out Fully-Differential 2-channel : INP1/INM1 - Ch1, INP2/INM2 - Ch2
# FSYNC = 48kHz (Output Data Sample Rate), BCLK = 12.288MHz (BCLK/FSYNC = 256)
################################################################
#
#
# Power up IOVDD and AVDD power supplies keeping SHDNZ pin voltage LOW
# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.
# Release SHDNZ to HIGH.
# Wait for 1ms
#

w a0 00 00 # Go to Page 0
w a0 02 81 # Exit Sleep mode, Enable VREG and DREG
d 10       # Wait for 16ms

w a0 00 01 # Go to Page 1
w a0 ED 80 # Enable Distortion Limiter, BOP, and Thermal Foldback
w a0 5E 90 # Enable VBAT and Temperature channel for diagnostics

w a0 00 19		# Go to page 0x19
w a0 60 7d 16 1b f8	# Limiter Attack Rate
w a0 64 43 ca d0 23	# Limiter Release Rate
w a0 7c 00 00 00 30	# Limiter Hold Counter
w a0 74 00 00 58 00	# Inflection Point
w a0 6c 01 1f 3c 9a	# Limiter Threshold Maximum
w a0 70 00 03 9d b8	# Limiter Threshold Minimum
w a0 78 10 00 00 00 	# Limiter Slope

w a0 00 01		# Go to page 0x1a
w a0 14 78 d6 fc 9f	# BOP Attack Rate
w a0 18 40 bd b7 c0	# BOP Release Rate
w a0 1c 00 00 00 60	# BOP Hold Counter 
w a0 20 00 00 58 00	# BOP Voltage Threshold 1 (CT1)
w a0 28 00 00 18 00 	# BOP Voltage Threshold 2 (CT2)
w a0 24 2d 4e fb d6	# BOP Threshold 1 (G1)
w a0 2c 06 66 66 66 	# BOP Threshold 2 (G2)

w a0 30 78 d6 fc 9f	# Thermal Attack Rate
w a0 34 40 bd b7 c0	# Thermal Release Rate
w a0 38 00 00 00 60	# Thermal Hold Counter 
w a0 3c 00 00 a0 00	# Temperature Threshold
w a0 40 04 0c 37 14 	# Max Attenuation Threshold
w a0 44 f0 00 00 00 	# Thermal Slope

w a0 00 00 # Go to Page 0
w a0 76 0c # Enable DAC Channels
w a0 78 40 # DAC Power Up