表 5-1 是 TAx5xxx-Q1 器件的示例脚本，基于应用程序示例部分所述的参数。

EVM1 示例脚本：

# Key: w a0 XX YY ==> write to I2C address 0xa0, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
# See the corresponding EVM user guide for jumper settings and audio connections.
#
# Line-Out Fully-Differential 2-channel : INP1/INM1 - Ch1, INP2/INM2 - Ch2
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 12.288 MHz (BCLK/FSYNC = 256)
################################################################### 
Power up IOVDD and AVDD power supplies keeping SHDNZ pin voltage LOW
# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.# Release SHDNZ to HIGH.
# Wait for 1ms
#
w a0 00 00  #Go to page 0
w a0 01 01  # Software reset
w a0 02 09  # Come out of sleep mode, enable DREG, VREF
###############
w a0 06 50  # Set HP cap charging time to 2ms
w a0 72 1a  # Enable ADC soft stepping
w a0 73 1a  # Enable DAC soft stepping
w a0 00 00  # Go to page 0
w a0 1b 48  # Enable bus keeper and HI-Z output
w a0 28 20  # CH1 data in slot 0
w a0 29 21  # Ch2 data in slot 1
w a0 25 25  # ICLA TX data on slot 5
w a0 2d 64  # ICLA RX Data on slot 4
################
w a0 00 01           # Go to page 1
w a0 2d 80           # Enable distortion limiter
w a0 53 90           # VBAT Ch enable for diagnostics
w a0 00 19           # Go to page 25
w a0 60 78 d6 fc 9f  # Attack rate
w a0 74 00 00 48 00  # 9V inflection point 
w a0 6c 01 69 9c 0f  # 0 dB Limiter Thr Max
w a0 64 40 bd b7 c0  # Release rate 
w a0 70 00 14 55 b6  # -25dB Limiter Thr Min
w a0 78 10 00 00 00  # Slope 1 V/V
##############
w a0 00 00  # Go to page 0
w a0 76 cf  # DAC CHs enabled
w a0 78 c0  # ADC & DAC powerup

EVM2 示例脚本：

# Key: w a1 XX YY ==> write to I2C address 0xa1, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
# See the corresponding EVM user guide for jumper settings and audio connections.
#
# Line-Out Fully-Differential 2-channel : INP1/INM1 - Ch1, INP2/INM2 - Ch2
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 12.288 MHz (BCLK/FSYNC = 256)
################################################################### 
Power up IOVDD and AVDD power supplies keeping SHDNZ pin voltage LOW
# Wait for IOVDD and AVDD power supplies to settle to steady state operating voltage range.# Release SHDNZ to HIGH.
# Wait for 1ms
#
w a1 00 00  #Go to page 0
w a1 01 01  # Software reset
w a1 02 09  # Come out of sleep mode, enable DREG, VREF
###############
w a1 06 50  # Set HP cap charging time to 2ms
w a1 72 1a  # Enable ADC soft stepping
w a1 73 1a  # Enable DAC soft stepping
w a1 00 00  # Go to page 0
w a1 1b 48  # Enable bus keeper and HI-Z output
w a1 28 22  # CH1 data in slot 2
w a1 29 23  # CH2 data in slot 3
w a1 25 24  # ICLA TX data on slot 4
w a1 2d 65  # ICLA RX Data on slot 5
################
w a1 00 01           # Go to page 1
w a1 2d 80           # Enable distortion limiter
w a1 53 90           # VBAT Ch enable for diagnostics
w a1 00 19           # Go to page 25
w a1 60 78 d6 fc 9f  # Attack rate
w a1 74 00 00 48 00  # 9V inflection point 
w a1 6c 00 cb 59 18  # -5dB Limiter Thr Max
w a1 64 40 bd b7 c0  # Release rate
w a1 70 00 01 24 bd  # -50dB Limiter Thr Min
w a1 78 20 00 00 00  # Slope 2 V/V
##############
w a1 00 00  # Go to page 0
w a1 76 cf  # DAC CHs enabled
w a1 78 c0  # ADC & DAC powerup