ZHCS009J November   2010  – September 2021 TMS320F28062 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28066-Q1 , TMS320F28067 , TMS320F28067-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1. 3.1 功能方框图
    2. 3.2 系统器件图
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 TMS320F2806x Current Consumption at 90-MHz SYSCLKOUT
      2. 7.5.2 Reducing Current Consumption
      3. 7.5.3 Current Consumption Graphs (VREG Enabled)
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics
      1. 7.7.1 PFP PowerPAD Package
      2. 7.7.2 PZP PowerPAD Package
      3. 7.7.3 PN Package
      4. 7.7.4 PZ Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  Debug Probe Connection Without Signal Buffering for the MCU
    10. 7.10 Parameter Information
      1. 7.10.1 Timing Parameter Symbology
      2. 7.10.2 General Notes on Timing Parameters
    11. 7.11 Test Load Circuit
    12. 7.12 Power Sequencing
      1. 7.12.1 Reset ( XRS) Timing Requirements
      2. 7.12.2 Reset ( XRS) Switching Characteristics
    13. 7.13 Clock Specifications
      1. 7.13.1 Device Clock Table
        1. 7.13.1.1 2806x Clock Table and Nomenclature (90-MHz Devices)
        2. 7.13.1.2 Device Clocking Requirements/Characteristics
        3. 7.13.1.3 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 7.13.2 Clock Requirements and Characteristics
        1. 7.13.2.1 XCLKIN Timing Requirements – PLL Enabled
        2. 7.13.2.2 XCLKIN Timing Requirements – PLL Disabled
        3. 7.13.2.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 7.14 Flash Timing
      1. 7.14.1 Flash/OTP Endurance for T Temperature Material
      2. 7.14.2 Flash/OTP Endurance for S Temperature Material
      3. 7.14.3 Flash/OTP Endurance for Q Temperature Material
      4. 7.14.4 Flash Parameters at 90-MHz SYSCLKOUT
      5. 7.14.5 Flash/OTP Access Timing
      6. 7.14.6 Flash Data Retention Duration
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1  CPU
      2. 8.1.2  Control Law Accelerator (CLA)
      3. 8.1.3  Viterbi, Complex Math, CRC Unit (VCU)
      4. 8.1.4  Memory Bus (Harvard Bus Architecture)
      5. 8.1.5  Peripheral Bus
      6. 8.1.6  Real-Time JTAG and Analysis
      7. 8.1.7  Flash
      8. 8.1.8  M0, M1 SARAMs
      9. 8.1.9  L4 SARAM, and L0, L1, L2, L3, L5, L6, L7, and L8 DPSARAMs
      10. 8.1.10 Boot ROM
        1. 8.1.10.1 Debug Boot
        2. 8.1.10.2 GetMode
        3. 8.1.10.3 Peripheral Pins Used by the Bootloader
      11. 8.1.11 Security
      12. 8.1.12 Peripheral Interrupt Expansion (PIE) Block
      13. 8.1.13 External Interrupts (XINT1 to XINT3)
      14. 8.1.14 Internal Zero Pin Oscillators, Oscillator, and PLL
      15. 8.1.15 Watchdog
      16. 8.1.16 Peripheral Clocking
      17. 8.1.17 Low-power Modes
      18. 8.1.18 Peripheral Frames 0, 1, 2, 3 (PFn)
      19. 8.1.19 General-Purpose Input/Output (GPIO) Multiplexer
      20. 8.1.20 32-Bit CPU-Timers (0, 1, 2)
      21. 8.1.21 Control Peripherals
      22. 8.1.22 Serial Port Peripherals
    2. 8.2 Memory Maps
    3. 8.3 Register Maps
    4. 8.4 Device Debug Registers
    5. 8.5 VREG, BOR, POR
      1. 8.5.1 On-chip VREG
        1. 8.5.1.1 Using the On-chip VREG
        2. 8.5.1.2 Disabling the On-chip VREG
      2. 8.5.2 On-chip Power-On Reset (POR) and Brownout Reset (BOR) Circuit
    6. 8.6 System Control
      1. 8.6.1 Internal Zero Pin Oscillators
      2. 8.6.2 Crystal Oscillator Option
      3. 8.6.3 PLL-Based Clock Module
      4. 8.6.4 USB and HRCAP PLL Module (PLL2)
      5. 8.6.5 Loss of Input Clock (NMI Watchdog Function)
      6. 8.6.6 CPU Watchdog Module
    7. 8.7 Low-power Modes Block
    8. 8.8 Interrupts
      1. 8.8.1 External Interrupts
        1. 8.8.1.1 External Interrupt Electrical Data/Timing
          1. 8.8.1.1.1 External Interrupt Timing Requirements
          2. 8.8.1.1.2 External Interrupt Switching Characteristics
    9. 8.9 Peripherals
      1. 8.9.1  CLA Overview
      2. 8.9.2  Analog Block
        1. 8.9.2.1 Analog-to-Digital Converter (ADC)
          1. 8.9.2.1.1 Features
          2. 8.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. 8.9.2.1.2.1 External ADC Start-of-Conversion Switching Characteristics
          3. 8.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. 8.9.2.1.3.1 ADC Electrical Characteristics
            2. 8.9.2.1.3.2 ADC Power Modes
            3. 8.9.2.1.3.3 Internal Temperature Sensor
              1. 8.9.2.1.3.3.1 Temperature Sensor Coefficient
            4. 8.9.2.1.3.4 ADC Power-Up Control Bit Timing
              1. 8.9.2.1.3.4.1 ADC Power-Up Delays
            5. 8.9.2.1.3.5 ADC Sequential and Simultaneous Timings
        2. 8.9.2.2 ADC MUX
        3. 8.9.2.3 Comparator Block
          1. 8.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. 8.9.2.3.1.1 Electrical Characteristics of the Comparator/DAC
      3. 8.9.3  Detailed Descriptions
      4. 8.9.4  Serial Peripheral Interface (SPI) Module
        1. 8.9.4.1 SPI Master Mode Electrical Data/Timing
          1. 8.9.4.1.1 SPI Master Mode External Timing (Clock Phase = 0)
          2. 8.9.4.1.2 SPI Master Mode External Timing (Clock Phase = 1)
        2. 8.9.4.2 SPI Slave Mode Electrical Data/Timing
          1. 8.9.4.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
          2. 8.9.4.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 8.9.5  Serial Communications Interface (SCI) Module
      6. 8.9.6  Multichannel Buffered Serial Port (McBSP) Module
        1. 8.9.6.1 McBSP Electrical Data/Timing
          1. 8.9.6.1.1 McBSP Transmit and Receive Timing
            1. 8.9.6.1.1.1 McBSP Timing Requirements
            2. 8.9.6.1.1.2 McBSP Switching Characteristics
          2. 8.9.6.1.2 McBSP as SPI Master or Slave Timing
            1. 8.9.6.1.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. 8.9.6.1.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. 8.9.6.1.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. 8.9.6.1.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. 8.9.6.1.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. 8.9.6.1.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. 8.9.6.1.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. 8.9.6.1.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      7. 8.9.7  Enhanced Controller Area Network (eCAN) Module
      8. 8.9.8  Inter-Integrated Circuit (I2C)
        1. 8.9.8.1 I2C Electrical Data/Timing
          1. 8.9.8.1.1 I2C Timing Requirements
          2. 8.9.8.1.2 I2C Switching Characteristics
      9. 8.9.9  Enhanced Pulse Width Modulator (ePWM) Modules (ePWM1 to ePWM8)
        1. 8.9.9.1 ePWM Electrical Data/Timing
          1. 8.9.9.1.1 ePWM Timing Requirements
          2. 8.9.9.1.2 ePWM Switching Characteristics
        2. 8.9.9.2 Trip-Zone Input Timing
          1. 8.9.9.2.1 Trip-Zone Input Timing Requirements
      10. 8.9.10 High-Resolution PWM (HRPWM)
        1. 8.9.10.1 HRPWM Electrical Data/Timing
          1. 8.9.10.1.1 High-Resolution PWM Characteristics
      11. 8.9.11 Enhanced Capture Module (eCAP1)
        1. 8.9.11.1 eCAP Electrical Data/Timing
          1. 8.9.11.1.1 Enhanced Capture (eCAP) Timing Requirement
          2. 8.9.11.1.2 eCAP Switching Characteristics
      12. 8.9.12 High-Resolution Capture Modules (HRCAP1 to HRCAP4)
        1. 8.9.12.1 HRCAP Electrical Data/Timing
          1. 8.9.12.1.1 High-Resolution Capture (HRCAP) Timing Requirements
      13. 8.9.13 Enhanced Quadrature Encoder Modules (eQEP1, eQEP2)
        1. 8.9.13.1 eQEP Electrical Data/Timing
          1. 8.9.13.1.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
          2. 8.9.13.1.2 eQEP Switching Characteristics
      14. 8.9.14 JTAG Port
      15. 8.9.15 General-Purpose Input/Output (GPIO) MUX
        1. 8.9.15.1 GPIO Electrical Data/Timing
          1. 8.9.15.1.1 GPIO Output Timing
            1. 8.9.15.1.1.1 General-Purpose Output Switching Characteristics
          2. 8.9.15.1.2 GPIO Input Timing
            1. 8.9.15.1.2.1 General-Purpose Input Timing Requirements
          3. 8.9.15.1.3 Sampling Window Width for Input Signals
          4. 8.9.15.1.4 Low-Power Mode Wakeup Timing
            1. 8.9.15.1.4.1 IDLE Mode Timing Requirements
            2. 8.9.15.1.4.2 IDLE Mode Switching Characteristics
            3. 8.9.15.1.4.3 STANDBY Mode Timing Requirements
            4. 8.9.15.1.4.4 STANDBY Mode Switching Characteristics
            5. 8.9.15.1.4.5 HALT Mode Timing Requirements
            6. 8.9.15.1.4.6 HALT Mode Switching Characteristics
      16. 8.9.16 Universal Serial Bus (USB)
        1. 8.9.16.1 USB Electrical Data/Timing
          1. 8.9.16.1.1 USB Input Ports DP and DM Timing Requirements
          2. 8.9.16.1.2 USB Output Ports DP and DM Switching Characteristics
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Device and Development Support Tool Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 术语表
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

8.9.9 Enhanced Pulse Width Modulator (ePWM) Modules (ePWM1 to ePWM8)

The devices contain up to eight enhanced PWM (ePWM) modules. Figure 8-48 shows a block diagram of multiple ePWM modules. Figure 8-49 shows the signal interconnections with the ePWM.

Table 8-33 and Table 8-34 show the complete ePWM register set per module.

GUID-A9688EA9-7B50-4CF6-BC4D-2A0B77C44602-low.gif
This signal exists only on devices with an eQEP1 module.
Figure 8-48 ePWM
Table 8-33 ePWM1–ePWM4 Control and Status Registers
NAMEePWM1ePWM2ePWM3ePWM4SIZE (×16)/
#SHADOW		DESCRIPTION
TBCTL0x68000x68400x68800x68C01/0Time Base Control Register
TBSTS0x68010x68410x68810x68C11/0Time Base Status Register
TBPHSHR0x68020x68420x68820x68C21/0Time Base Phase HRPWM Register
TBPHS0x68030x68430x68830x68C31/0Time Base Phase Register
TBCTR0x68040x68440x68840x68C41/0Time Base Counter Register
TBPRD0x68050x68450x68850x68C51/1Time Base Period Register Set
TBPRDHR0x68060x68460x68860x68C61/1Time Base Period High-Resolution Register(1)
CMPCTL0x68070x68470x68870x68C71/0Counter Compare Control Register
CMPAHR0x68080x68480x68880x68C81/1Time Base Compare A HRPWM Register
CMPA0x68090x68490x68890x68C91/1Counter Compare A Register Set
CMPB0x680A0x684A0x688A0x68CA1/1Counter Compare B Register Set
AQCTLA0x680B0x684B0x688B0x68CB1/0Action Qualifier Control Register For Output A
AQCTLB0x680C0x684C0x688C0x68CC1/0Action Qualifier Control Register For Output B
AQSFRC0x680D0x684D0x688D0x68CD1/0Action Qualifier Software Force Register
AQCSFRC0x680E0x684E0x688E0x68CE1/1Action Qualifier Continuous S/W Force Register Set
DBCTL0x680F0x684F0x688F0x68CF1/1Dead-Band Generator Control Register
DBRED0x68100x68500x68900x68D01/0Dead-Band Generator Rising Edge Delay Count Register
DBFED0x68110x68510x68910x68D11/0Dead-Band Generator Falling Edge Delay Count Register
TZSEL0x68120x68520x68920x68D21/0Trip Zone Select Register(1)
TZDCSEL0x68130x68530x68930x68D31/0Trip Zone Digital Compare Register
TZCTL0x68140x68540x68940x68D41/0Trip Zone Control Register(1)
TZEINT0x68150x68550x68950x68D51/0Trip Zone Enable Interrupt Register(1)
TZFLG0x68160x68560x68960x68D61/0Trip Zone Flag Register (1)
TZCLR0x68170x68570x68970x68D71/0Trip Zone Clear Register(1)
TZFRC0x68180x68580x68980x68D81/0Trip Zone Force Register(1)
ETSEL0x68190x68590x68990x68D91/0Event Trigger Selection Register
ETPS0x681A0x685A0x689A0x68DA1/0Event Trigger Prescale Register
ETFLG0x681B0x685B0x689B0x68DB1/0Event Trigger Flag Register
ETCLR0x681C0x685C0x689C0x68DC1/0Event Trigger Clear Register
ETFRC0x681D0x685D0x689D0x68DD1/0Event Trigger Force Register
PCCTL0x681E0x685E0x689E0x68DE1/0PWM Chopper Control Register
HRCNFG0x68200x68600x68A00x68E01/0HRPWM Configuration Register(1)
HRMSTEP0x6826---1/0HRPWM MEP Step Register
HRPCTL0x68280x68680x68A80x68E81/0High-resolution Period Control Register(1)
TBPRDHRM0x682A0x686A0x68AA0x68EA1/W(2)Time Base Period HRPWM Register Mirror
TBPRDM0x682B0x686B0x68AB0x68EB1/W(2)Time Base Period Register Mirror
CMPAHRM0x682C0x686C0x68AC0x68EC1/W(2)Compare A HRPWM Register Mirror
CMPAM0x682D0x686D0x68AD0x68ED1/W(2)Compare A Register Mirror
DCTRIPSEL0x68300x68700x68B00x68F01/0Digital Compare Trip Select Register (1)
DCACTL0x68310x68710x68B10x68F11/0Digital Compare A Control Register(1)
DCBCTL0x68320x68720x68B20x68F21/0Digital Compare B Control Register(1)
DCFCTL0x68330x68730x68B30x68F31/0Digital Compare Filter Control Register(1)
DCCAPCT0x68340x68740x68B40x68F41/0Digital Compare Capture Control Register(1)
DCFOFFSET0x68350x68750x68B50x68F51/1Digital Compare Filter Offset Register
DCFOFFSETCNT0x68360x68760x68B60x68F61/0Digital Compare Filter Offset Counter Register
DCFWINDOW0x68370x68770x68B70x68F71/0Digital Compare Filter Window Register
DCFWINDOWCNT0x68380x68780x68B80x68F81/0Digital Compare Filter Window Counter Register
DCCAP0x68390x68790x68B90x68F91/1Digital Compare Counter Capture Register
(1) Registers that are EALLOW protected.
(2) W = Write to shadow register
Table 8-34 ePWM5–ePWM8 Control and Status Registers
NAMEePWM5ePWM6ePWM7ePWM8SIZE (×16)/
#SHADOW		DESCRIPTION
TBCTL0x69000x69400x69800x69C01/0Time Base Control Register
TBSTS0x69010x69410x69810x69C11/0Time Base Status Register
TBPHSHR0x69020x69420x69820x69C21/0Time Base Phase HRPWM Register
TBPHS0x69030x69430x69830x69C31/0Time Base Phase Register
TBCTR0x69040x69440x69840x69C41/0Time Base Counter Register
TBPRD0x69050x69450x69850x69C51/1Time Base Period Register Set
TBPRDHR0x69060x69460x69860x69C61/1Time Base Period High-Resolution Register(1)
CMPCTL0x69070x69470x69870x69C71/0Counter Compare Control Register
CMPAHR0x69080x69480x69880x69C81/1Time Base Compare A HRPWM Register
CMPA0x69090x69490x69890x69C91/1Counter Compare A Register Set
CMPB0x690A0x694A0x698A0x69CA1/1Counter Compare B Register Set
AQCTLA0x690B0x694B0x698B0x69CB1/0Action Qualifier Control Register For Output A
AQCTLB0x690C0x694C0x698C0x69CC1/0Action Qualifier Control Register For Output B
AQSFRC0x690D0x694D0x698D0x69CD1/0Action Qualifier Software Force Register
AQCSFRC0x690E0x694E0x698E0x69CE1/1Action Qualifier Continuous S/W Force Register Set
DBCTL0x690F0x694F0x698F0x69CF1/1Dead-Band Generator Control Register
DBRED0x69100x69500x69900x69D01/0Dead-Band Generator Rising Edge Delay Count Register
DBFED0x69110x69510x69910x69D11/0Dead-Band Generator Falling Edge Delay Count Register
TZSEL0x69120x69520x69920x69D21/0Trip Zone Select Register(1)
TZDCSEL0x69130x69530x69930x69D31/0Trip Zone Digital Compare Register
TZCTL0x69140x69540x69940x69D41/0Trip Zone Control Register(1)
TZEINT0x69150x69550x69950x69D51/0Trip Zone Enable Interrupt Register(1)
TZFLG0x69160x69560x69960x69D61/0Trip Zone Flag Register (1)
TZCLR0x69170x69570x69970x69D71/0Trip Zone Clear Register(1)
TZFRC0x69180x69580x69980x69D81/0Trip Zone Force Register(1)
ETSEL0x69190x69590x69990x69D91/0Event Trigger Selection Register
ETPS0x691A0x695A0x699A0x69DA1/0Event Trigger Prescale Register
ETFLG0x691B0x695B0x699B0x69DB1/0Event Trigger Flag Register
ETCLR0x691C0x695C0x699C0x69DC1/0Event Trigger Clear Register
ETFRC0x691D0x695D0x699D0x69DD1/0Event Trigger Force Register
PCCTL0x691E0x695E0x699E0x69DE1/0PWM Chopper Control Register
HRCNFG0x69200x69600x69A00x69E01/0HRPWM Configuration Register(1)
HRMSTEP----1/0HRPWM MEP Step Register
HRPCTL0x69280x69680x69A80x69E81/0High-resolution Period Control Register(1)
TBPRDHRM0x692A0x696A0x69AA0x69EA1/W(2)Time Base Period HRPWM Register Mirror
TBPRDM0x692B0x696B0x69AB0x69EB1/W(2)Time Base Period Register Mirror
CMPAHRM0x692C0x696C0x69AC0x69EC1/W(2)Compare A HRPWM Register Mirror
CMPAM0x692D0x696D0x69AD0x69ED1/W(2)Compare A Register Mirror
DCTRIPSEL0x69300x69700x69B00x69F01/0Digital Compare Trip Select Register (1)
DCACTL0x69310x69710x69B10x69F11/0Digital Compare A Control Register(1)
DCBCTL0x69320x69720x69B20x69F21/0Digital Compare B Control Register(1)
DCFCTL0x69330x69730x69B30x69F31/0Digital Compare Filter Control Register(1)
DCCAPCT0x69340x69740x69B40x69F41/0Digital Compare Capture Control Register(1)
DCFOFFSET0x69350x69750x69B50x69F51/1Digital Compare Filter Offset Register
DCFOFFSETCNT0x69360x69760x69B60x69F61/0Digital Compare Filter Offset Counter Register
DCFWINDOW0x69370x69770x69B70x69F71/0Digital Compare Filter Window Register
DCFWINDOWCNT0x69380x69780x69B80x69F81/0Digital Compare Filter Window Counter Register
DCCAP0x69390x69790x69B90x69F91/1Digital Compare Counter Capture Register
(1) Registers that are EALLOW protected.
(2) W = Write to shadow register
GUID-D31A9E48-A79E-4C54-9851-08872D710FE0-low.gif
These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the COMPxOUT and TZ signals.
This signal exists only on devices with an eQEP1 module.
Figure 8-49 ePWM Submodules Showing Critical Internal Signal Interconnections
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