ZHCS009J November 2010 – September 2021 TMS320F28062 , TMS320F28062-Q1 , TMS320F28062F , TMS320F28062F-Q1 , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28066-Q1 , TMS320F28067 , TMS320F28067-Q1 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069-Q1 , TMS320F28069F , TMS320F28069F-Q1 , TMS320F28069M , TMS320F28069M-Q1
PRODUCTION DATA
The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging I/O capability.
The device supports 45 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 8-38 shows the GPIO register mapping.
NAME | ADDRESS | SIZE (×16) | DESCRIPTION |
---|---|---|---|
GPIO CONTROL REGISTERS (EALLOW PROTECTED) | |||
GPACTRL | 0x6F80 | 2 | GPIO A Control Register (GPIO0 to 31) |
GPAQSEL1 | 0x6F82 | 2 | GPIO A Qualifier Select 1 Register (GPIO0 to 15) |
GPAQSEL2 | 0x6F84 | 2 | GPIO A Qualifier Select 2 Register (GPIO16 to 31) |
GPAMUX1 | 0x6F86 | 2 | GPIO A MUX 1 Register (GPIO0 to 15) |
GPAMUX2 | 0x6F88 | 2 | GPIO A MUX 2 Register (GPIO16 to 31) |
GPADIR | 0x6F8A | 2 | GPIO A Direction Register (GPIO0 to 31) |
GPAPUD | 0x6F8C | 2 | GPIO A Pullup Disable Register (GPIO0 to 31) |
GPBCTRL | 0x6F90 | 2 | GPIO B Control Register (GPIO32 to 44) |
GPBQSEL1 | 0x6F92 | 2 | GPIO B Qualifier Select 1 Register (GPIO32 to 44) |
GPBQSEL2 | 0x6F94 | 2 | GPIO B Qualifier Select 2 Register |
GPBMUX1 | 0x6F96 | 2 | GPIO B MUX 1 Register (GPIO32 to 44) |
GPBMUX2 | 0x6F98 | 2 | GPIO B MUX 2 Register (GPIO50 to 58) |
GPBDIR | 0x6F9A | 2 | GPIO B Direction Register (GPIO32 to 44) |
GPBPUD | 0x6F9C | 2 | GPIO B Pullup Disable Register (GPIO32 to 44) |
AIOMUX1 | 0x6FB6 | 2 | Analog, I/O mux 1 register (AIO0 to AIO15) |
AIODIR | 0x6FBA | 2 | Analog, I/O Direction Register (AIO0 to AIO15) |
GPIO DATA REGISTERS (NOT EALLOW PROTECTED) | |||
GPADAT | 0x6FC0 | 2 | GPIO A Data Register (GPIO0 to 31) |
GPASET | 0x6FC2 | 2 | GPIO A Data Set Register (GPIO0 to 31) |
GPACLEAR | 0x6FC4 | 2 | GPIO A Data Clear Register (GPIO0 to 31) |
GPATOGGLE | 0x6FC6 | 2 | GPIO A Data Toggle Register (GPIO0 to 31) |
GPBDAT | 0x6FC8 | 2 | GPIO B Data Register (GPIO32 to 44) |
GPBSET | 0x6FCA | 2 | GPIO B Data Set Register (GPIO32 to 44) |
GPBCLEAR | 0x6FCC | 2 | GPIO B Data Clear Register (GPIO32 to 44) |
GPBTOGGLE | 0x6FCE | 2 | GPIO B Data Toggle Register (GPIO32 to 44) |
AIODAT | 0x6FD8 | 2 | Analog I/O Data Register (AIO0 to AIO15) |
AIOSET | 0x6FDA | 2 | Analog I/O Data Set Register (AIO0 to AIO15) |
AIOCLEAR | 0x6FDC | 2 | Analog I/O Data Clear Register (AIO0 to AIO15) |
AIOTOGGLE | 0x6FDE | 2 | Analog I/O Data Toggle Register (AIO0 to AIO15) |
GPIO INTERRUPT AND LOW-POWER MODES SELECT REGISTERS (EALLOW PROTECTED) | |||
GPIOXINT1SEL | 0x6FE0 | 1 | XINT1 GPIO Input Select Register (GPIO0 to 31) |
GPIOXINT2SEL | 0x6FE1 | 1 | XINT2 GPIO Input Select Register (GPIO0 to 31) |
GPIOXINT3SEL | 0x6FE2 | 1 | XINT3 GPIO Input Select Register (GPIO0 to 31) |
GPIOLPMSEL | 0x6FE8 | 2 | LPM GPIO Select Register (GPIO0 to 31) |
There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn and GPxQSELn registers occurs to when the action is valid.
DEFAULT AT RESET PRIMARY I/O FUNCTION(1)(2) | PERIPHERAL SELECTION 1 | PERIPHERAL SELECTION 2 | PERIPHERAL SELECTION 3 | |
---|---|---|---|---|
GPAMUX1 REGISTER BITS | (GPAMUX1 BITS = 00) | (GPAMUX1 BITS = 01) | (GPAMUX1 BITS = 10) | (GPAMUX1 BITS = 11) |
1-0 | GPIO0 | EPWM1A (O) | Reserved | Reserved |
3-2 | GPIO1 | EPWM1B (O) | Reserved | COMP1OUT (O) |
5-4 | GPIO2 | EPWM2A (O) | Reserved | Reserved |
7-6 | GPIO3 | EPWM2B (O) | SPISOMIA (I/O) | COMP2OUT (O) |
9-8 | GPIO4 | EPWM3A (O) | Reserved | Reserved |
11-10 | GPIO5 | EPWM3B (O) | SPISIMOA (I/O) | ECAP1 (I/O) |
13-12 | GPIO6 | EPWM4A (O) | EPWMSYNCI (I) | EPWMSYNCO (O) |
15-14 | GPIO7 | EPWM4B (O) | SCIRXDA (I) | ECAP2 (I/O) |
17-16 | GPIO8 | EPWM5A (O) | Reserved | ADCSOCAO (O) |
19-18 | GPIO9 | EPWM5B (O) | SCITXDB (O) | ECAP3 (I/O) |
21-20 | GPIO10 | EPWM6A (O) | Reserved | ADCSOCBO (O) |
23-22 | GPIO11 | EPWM6B (O) | SCIRXDB (I) | ECAP1 (I/O) |
25-24 | GPIO12 | TZ1 (I) | SCITXDA (O) | SPISIMOB (I/O) |
27-26 | GPIO13 | TZ2 (I) | Reserved | SPISOMIB (I/O) |
29-28 | GPIO14 | TZ3 (I) | SCITXDB (O) | SPICLKB (I/O) |
31-30 | GPIO15 | ECAP2 (I/O) | SCIRXDB (I) | SPISTEB (I/O) |
GPAMUX2 REGISTER BITS | (GPAMUX2 BITS = 00) | (GPAMUX2 BITS = 01) | (GPAMUX2 BITS = 10) | (GPAMUX2 BITS = 11) |
1-0 | GPIO16 | SPISIMOA (I/O) | Reserved | TZ2 (I) |
3-2 | GPIO17 | SPISOMIA (I/O) | Reserved | TZ3 (I) |
5-4 | GPIO18 | SPICLKA (I/O) | SCITXDB (O) | XCLKOUT (O) |
7-6 | GPIO19/XCLKIN | SPISTEA (I/O) | SCIRXDB (I) | ECAP1 (I/O) |
9-8 | GPIO20 | EQEP1A (I) | MDXA (O) | COMP1OUT (O) |
11-10 | GPIO21 | EQEP1B (I) | MDRA (I) | COMP2OUT (O) |
13-12 | GPIO22 | EQEP1S (I/O) | MCLKXA (I/O) | SCITXDB (O) |
15-14 | GPIO23 | EQEP1I (I/O) | MFSXA (I/O) | SCIRXDB (I) |
17-16 | GPIO24 | ECAP1 (I/O) | EQEP2A(3) (I) | SPISIMOB (I/O) |
19-18 | GPIO25 | ECAP2 (I/O) | EQEP2B(3) (I) | SPISOMIB (I/O) |
21-20 | GPIO26(4) | ECAP3 (I/O) | EQEP2I(3) (I/O) | SPICLKB (I/O) |
23-22 | GPIO27(4) | HRCAP2 (I) | EQEP2S(3) (I/O) | SPISTEB (I/O) |
25-24 | GPIO28 | SCIRXDA (I) | SDAA (I/OD) | TZ2 (I) |
27-26 | GPIO29 | SCITXDA (O) | SCLA (I/OD) | TZ3 (I) |
29-28 | GPIO30 | CANRXA (I) | EQEP2I(3) (I/O) | EPWM7A (O) |
31-30 | GPIO31 | CANTXA (O) | EQEP2S(3) (I/O) | EPWM8A (O) |