米6体育平台手机版

ZHCS114E march 2011 – february 2023 ADS4222 , ADS4225 , ADS4226 , ADS4242 , ADS4245 , ADS4246

PRODUCTION DATA

7.9 Timing Requirements: LVDS and CMOS Modes⁽¹⁾

Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 160MSPS, sine wave input clock, 1.5 V_PP clock amplitude, C_LOAD = 5 pF⁽²⁾, and R_LOAD = 100 Ω⁽³⁾, unless otherwise noted. Minimum and maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V.

			MIN	NOM	MAX	UNIT
t_A	Aperture delay		0.5	0.8	1.1	ns
	Aperture delay matching	Between the two channels of the same device		±70		ps
	Variation of aperture delay	Between two devices at the same temperature and DRVDD supply		±150		ps
t_J	Aperture jitter			140		f_S rms
	Wakeup time	Time to valid data after coming out of STANDBY mode		50	100	µs
	Wakeup time	Time to valid data after coming out of GLOBAL power-down mode		100	500	µs
	ADC latency⁽⁷⁾	Default latency after reset		16		Clock cycles
	ADC latency⁽⁷⁾	Digital functions enabled (EN DIGITAL = 1)		24		Clock cycles
DDR LVDS MODE⁽⁴⁾
t_SU	Data setup time	Data valid⁽⁵⁾ to zero-crossing of CLKOUTP	1.5	2		ns
t_H	Data hold time	Zero-crossing of CLKOUTP to data becoming invalid⁽⁵⁾	0.35	0.6		ns
t_PDI	Clock propagation delay	Input clock rising edge cross-over to output clock rising edge cross-over	5	6.1	7.5	ns
	LVDS bit clock duty cycle	Duty cycle of differential clock, (CLKOUTP-CLKOUTM)		49%
t_RISE, t_FALL	Data rise time, Data fall time	Rise time measured from –100 mV to +100 mV Fall time measured from +100 mV to –100 mV 1MSPS ≤ Sampling frequency ≤ 160MSPS		0.13		ns
t_CLKRISE, t_CLKFALL	Output clock rise time, Output clock fall time	Rise time measured from –100 mV to +100 mV Fall time measured from +100 mV to –100 mV 1MSPS ≤ Sampling frequency ≤ 160MSPS		0.13		ns
PARALLEL CMOS MODE
t_SU	Data setup time	Data valid⁽⁶⁾ to zero-crossing of CLKOUT	1.6	2.5		ns
t_H	Data hold time	Zero-crossing of CLKOUT to data becoming invalid⁽⁶⁾	2.3	2.7		ns
t_PDI	Clock propagation delay	Input clock rising edge cross-over to output clock rising edge cross-over	4.5	6.4	8.5	ns
	Output clock duty cycle	Duty cycle of output clock, CLKOUT 1MSPS ≤ Sampling frequency ≤ 160MSPS		46%
t_RISE, t_FALL	Data rise time, Data fall time	Rise time measured from 20% to 80% of DRVDD Fall time measured from 80% to 20% of DRVDD 1MSPS ≤ Sampling frequency ≤ 160MSPS		1		ns
t_CLKRISE, t_CLKFALL	Output clock rise time Output clock fall time	Rise time measured from 20% to 80% of DRVDD Fall time measured from 80% to 20% of DRVDD 1MSPS ≤ Sampling frequency ≤ 160MSPS		1		ns

(1) Timing parameters are ensured by design and characterization and not tested in production.

(2) C_LOAD is the effective external single-ended load capacitance between each output pin and ground

(3) R_LOAD is the differential load resistance between the LVDS output pair.

(4) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.

(5) Data valid refers to a logic high of +100 mV and a logic low of –100 mV.

(6) Data valid refers to a logic high of 1.26 V and a logic low of 0.54 V

(7) At higher frequencies, t_PDI is greater than one clock period and overall latency = ADC latency + 1.

7.9 Timing Requirements: LVDS and CMOS Modes(1)

7.9 Timing Requirements: LVDS and CMOS Modes⁽¹⁾