At T_A = 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5-V_PP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, High-Performance Mode disabled, 0-dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.

Figure 7-88 FFT for 20-MHz Input Signal

Figure 7-90 FFT for Two-Tone Input Signal

Figure 7-92 SNR vs Input Frequency

Figure 7-94 SFDR vs Gain and Input Frequency

Figure 7-96 Performance vs Input Amplitude

Figure 7-98 SFDR vs Temperature and AVDD Supply

Figure 7-100 Performance vs DRVDD Supply Voltage

Figure 7-102 Performance vs Input Clock Amplitude

Figure 7-89 FFT for 300-MHz Input Signal

Figure 7-91 SFDR vs Input Frequency

Figure 7-93 SNR vs Input Frequency (CMOS)

Figure 7-95 Performance vs Input Amplitude

Figure 7-97 Performance vs Input Common-Mode Voltage

Figure 7-99 SNR vs Temperature and AVDD Supply

Figure 7-101 Performance vs Input Clock Amplitude

Figure 7-103 Performance vs Input Clock Duty Cycle