The ADS424x/422x clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5-kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or ac-coupling for LVPECL and LVDS clock sources are shown in Figure 8-10, Figure 8-11 and Figure 8-12. The internal clock buffer is shown in Figure 8-13.

R_T = termination resister, if necessary.

Figure 8-10 Differential Sine-Wave Clock Driving Circuit

Figure 8-12 LVPECL Clock Driving Circuit

Figure 8-11 LVDS Clock Driving Circuit

C_EQ is 1 pF to 3 pF, and is the equivalent input capacitance of the clock buffer.

Figure 8-13 Internal Clock Buffer

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 8-14. For best performance, the clock inputs must be driven differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input.

Figure 8-14 Single-Ended Clock Driving Circuit