米6体育平台手机版

ZHCS114E march 2011 – february 2023 ADS4222 , ADS4225 , ADS4226 , ADS4242 , ADS4245 , ADS4246

PRODUCTION DATA

7.8 Digital Characteristics

At AVDD = 1.8 V and DRVDD = 1.8 V, unless otherwise noted. DC specifications refer to the condition where the digital outputs do not switch, but are permanently at a valid logic level 0 or 1.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3)⁽¹⁾
High-level input voltage		All digital inputs support 1.8-V and 3.3-V CMOS logic levels	1.3			V
Low-level input voltage		All digital inputs support 1.8-V and 3.3-V CMOS logic levels			0.4	V
High-level input current	SDATA, SCLK⁽²⁾	V_HIGH = 1.8 V		10		µA
High-level input current	SEN⁽³⁾	V_HIGH = 1.8 V		0		µA
Low-level input current	SDATA, SCLK	V_LOW = 0 V		0		µA
Low-level input current	SEN	V_LOW = 0 V		10		µA
DIGITAL OUTPUTS, CMOS INTERFACE (DA[13:0], DB[13:0], CLKOUT, SDOUT)
High-level output voltage			DRVDD – 0.1	DRVDD		V
Low-level output voltage				0	0.1	V
Output capacitance (internal to device)						pF
DIGITAL OUTPUTS, LVDS INTERFACE
High-level output differential voltage	V_ODH	With an external 100-Ω termination	270	350	430	mV
Low-level output differential voltage	V_ODL	With an external 100-Ω termination	–430	–350	–270	mV
Output common-mode voltage	V_OCM		0.9	1.05	1.25	V

(1) SCLK, SDATA, and SEN function as digital input pins in serial configuration mode.

(2) SDATA, SCLK have internal 150-kΩ pull-down resistor.

(3) SEN has an internal 150-kΩ pull-up resistor to AVDD. Because the pull-up is weak, SEN can also be driven by 1.8-V or 3.3-V CMOS buffers.