10.1 Layout Guidelines

• The optimum placement is as close to the connector as possible.
  • EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures.
  • The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector.
  • Keep traces between the connector and TPD4S014 on the same layer as TPD4S014.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible.
  • Electric fields tend to build up on corners, increasing EMI coupling.

When designing layout for TPD4S014, note that V_BUSOUT and V_BUS pins allow for extra wide traces for good power delivery. In the example shown, these pins are routed with 25 mil (0.64 mm) wide traces. Place the V_BUSOUT and V_BUS capacitors as close to the device pins as possible. Pull ACK up to the Processor logic level high with a resistor. Use external and internal ground planes and stitch them together with VIAs as close to the GND pins of TPD4S014 as possible. This allows for a low impedance path to ground so that the device can properly dissipate any ESD events.

10.2 Layout Example

Figure 17. Layout Recommendation