米6体育平台手机版

ZHCS158C July 2012 – January 2017 ADS1299 , ADS1299-4 , ADS1299-6

PRODUCTION DATA.

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

		MIN	MAX	UNIT
Voltage	AVDD to AVSS	–0.3	5.5	V
	DVDD to DGND	–0.3	3.9
	AVSS to DGND	–3	0.2
	VREFP to AVSS	–0.3	AVDD + 0.3
	VREFN to AVSS	–0.3	AVDD + 0.3
	Analog input	AVSS – 0.3	AVDD + 0.3
	Digital input	DGND – 0.3	DVDD + 0.3
Current	Input, continuous, any pin except power supply pins⁽²⁾	–10	10	mA
Temperature	Junction, T_J		150	°C
Temperature	Storage, T_stg	–60	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Input pins are diode-clamped to the power-supply rails. Limit the input current to 10 mA or less if the analog input voltage exceeds AVDD + 0.3 V or is less than AVSS – 0.3 V, or if the digital input voltage exceeds DVDD + 0.3 V or is less than DGND – 0.3 V.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
POWER SUPPLY
	Analog power supply	AVDD to AVSS	4.75	5	5.25	V
	Digital power supply	DVDD to DGND	1.8	1.8	3.6	V
	Analog to Digital supply	AVDD – DVDD	–2.1		3.6	V
ANALOG INPUTS
	Full-scale differential input voltage	V_INxP – V_INxN		±V_REF / gain		V
V_CM	Input common-mode range	(V_INxP + V_INxN) / 2	See the Input Common-Mode Range subsection of the PGA Settings and Input Range section
VOLTAGE REFERENCE INPUTS
V_REF	Reference input voltage	V_REF = (V_VREFP – V_VREFN)		4.5		V
VREFN	Negative input			AVSS		V
VREFP	Positive input			AVSS + 4.5		V
CLOCK INPUT
f_CLK	External clock input frequency	CLKSEL pin = 0	1.5	2.048	2.25	MHz
DIGITAL INPUTS
	Input voltage		DGND – 0.1		DVDD + 0.1	V
TEMPERATURE RANGE
T_A	Operating temperature range		–40		85	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS1299-4, ADS1299-6, ADS1299	UNIT
		PAG (TQFP)
		64 PINS
R_θJA	Junction-to-ambient thermal resistance	46.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	5.8	°C/W
R_θJB	Junction-to-board thermal resistance	19.6	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	19.2	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

Minimum and maximum specifications apply from T_A = –40°C to 85°C. Typical specifications are at T_A = +25°C. All specifications are at AVDD – AVSS = 5 V, DVDD = 3.3 V, V_REF = 4.5 V, external f_CLK = 2.048 MHz, data rate = 250 SPS, and gain = 12 (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
	Input capacitance				20		pF
	Input bias current		T_A = +25°C, InxP and INxN = 2.5 V			±300	pA
	Input bias current		T_A = –40°C to +85°C, InxP and INxN = 2.5 V		±300		pA
	DC input impedance		No lead-off	1000			MΩ
	DC input impedance		Current source lead-off detection (I_LEADOFF = 6 nA)		500		MΩ
PGA PERFORMANCE
	Gain settings			1, 2, 4, 6, 8, 12, 24
BW	Bandwidth			See Table 5
ADC PERFORMANCE
	Resolution			24			Bits
DR	Data rate		f_CLK = 2.048 MHz	250		16000	SPS
DC CHANNEL PERFORMANCE
	Input-referred noise (0.01 Hz to 70 Hz)		10 seconds of data, gain = 24⁽¹⁾		1		μV_PP
			250 points, 1 second of data, gain = 24, T_A = +25°C		1	1.35
			250 points, 1 second of data, gain = 24, T_A = –40°C to +85°C		1	1.6
			All other sample rates and gain settings	See Noise Measurements
INL	Integral nonlinearity		Full-scale with gain = 12, best fit		8		ppm
	Offset error				60		μV
	Offset error drift				80		nV/°C
	Gain error		Excluding voltage reference error		0.1	±0.5	% of FS
	Gain drift		Excluding voltage reference drift		3		ppm/°C
	Gain match between channels				0.2		% of FS
AC CHANNEL PERFORMANCE
CMRR	Common-mode rejection ratio		f_CM = 50 Hz and 60 Hz⁽²⁾	–110	–120		dB
PSRR	Power-supply rejection ratio		f_PS = 50 Hz and 60 Hz		96		dB
	Crosstalk		f_IN = 50 Hz and 60 Hz		–110		dB
SNR	Signal-to-noise ratio		V_IN = –2 dBFs, f_IN = 10-Hz input, gain = 12		121		dB
THD	Total harmonic distortion		V_IN = –0.5 dBFs, f_IN = 10 Hz		–99		dB
PATIENT BIAS AMPLIFIER
	Integrated noise		BW = 150 Hz		2		μV_RMS
	Gain bandwidth product		50-kΩ \|\| 10-pF load, gain = 1		100		kHz
	Slew rate		50-kΩ \|\| 10-pF load, gain = 1		0.07		V/μs
THD	Total harmonic distortion		f_IN = 10 Hz, gain = 1		–80		dB
	Common-mode input range			AVSS + 0.3		AVDD – 0.3	V
	Short-circuit current				1.1		mA
	Quiescent power consumption				20		μA
LEAD-OFF DETECT
	Frequency		Continuous	At dc, f_DR / 4, see Register Maps for settings			Hz
	Frequency		One time or periodic	7.8, 31.2			Hz
	Current		ILEAD_OFF[1:0] = 00		6		nA
			ILEAD_OFF[1:0] = 01		24		nA
			ILEAD_OFF[1:0] = 10		6		μA
			ILEAD_OFF[1:0] = 11		24		μA
	Current accuracy				±20%
	Comparator threshold accuracy				±30		mV
EXTERNAL REFERENCE
	Input impedance				5.6		kΩ
INTERNAL REFERENCE
V_REF	Internal reference voltage				4.5		V
	V_REF accuracy				±0.2%
	Drift		T_A = –40°C to +85°C		35		ppm/°C
	Start-up time				150		ms
SYSTEM MONITORS
	Reading error	Analog supply			2%
	Reading error	Digital supply			2%
	Device wake up		From power-up to DRDY low		150		ms
	Device wake up		STANDBY mode		31.25		µs
	Temperature sensor reading	Voltage	T_A = +25°C		145		mV
	Temperature sensor reading	Coefficient			490		μV/°C
	Test signal	Signal frequency	See Register Maps section for settings	f_CLK / 2²¹, f_CLK / 2²⁰			Hz
		Signal voltage	See Register Maps section for settings	±1, ±2			mV
		Accuracy			±2%
CLOCK
	Internal oscillator clock frequency		Nominal frequency		2.048		MHz
	Internal clock accuracy		T_A = +25°C			±0.5%
	Internal clock accuracy		T_A = –40°C to +85°C			±2.5%
	Internal oscillator start-up time				20		μs
	Internal oscillator power consumption				120		μW
DIGITAL INPUT/OUTPUT (DVDD = 1.8 V to 3.6 V)
V_IH	High-level input voltage			0.8 DVDD		DVDD + 0.1	V
V_IL	Low-level input voltage			–0.1		0.2 DVDD	V
V_OH	High-level output voltage		I_OH = –500 μA	0.9 DVDD			V
V_OL	Low-level output voltage		I_OL = +500 μA			0.1 DVDD	V
	Input current		0 V < V_DigitalInput < DVDD	–10		10	μA
SUPPLY CURRENT (Bias Turned Off)
I_AVDD	AVDD current	ADS1299-4	Normal mode, AVDD – AVSS = 5 V		4.06		mA
		ADS1299-6			5.57
		ADS1299			7.14
I_DVDD	DVDD current	ADS1299-4	Normal mode, DVDD = 3.3 V		0.54		mA
		ADS1299-6			0.66
		ADS1299			1
		ADS1299-4	Normal mode, DVDD = 1.8 V		0.27
		ADS1299-6			0.34
		ADS1299			0.5
POWER DISSIPATION (Analog Supply = 5 V, Bias Amplifiers Turned Off)
	Power dissipation	ADS1299-4	Normal mode		22	24	mW
			Power-down		10		µW
			Standby mode, internal reference		5.1		mW
		ADS1299-6	Normal mode		30	33	mW
			Power-down		10		µW
			Standby mode, internal reference		5.1		mW
		ADS1299	Normal mode		39	42	mW
			Power-down		10		µW
			Standby mode, internal reference		5.1		mW

(1) Noise data measured in a 10-second interval. Test not performed in production. Input-referred noise is calculated with the input shorted (without electrode resistance) over a 10-second interval.

(2) CMRR is measured with a common-mode signal of AVSS + 0.3 V to AVDD – 0.3 V. The values indicated are the minimum of the eight channels.

7.6 Timing Requirements: Serial Interface

over operating ambient temperature range (unless otherwise noted)

		2.7 V ≤ DVDD ≤ 3.6 V		1.8 V ≤ DVDD ≤ 2.0 V		UNIT
		MIN	MAX	MIN	MAX	UNIT
t_CLK	Master clock period	414	666	414	666	ns
t_CSSC	Delay time, CS low to first SCLK	6		17		ns
t_SCLK	SCLK period	50		66.6		ns
t_{SPWH, L}	Pulse duration, SCLK pulse duration, high or low	15		25		ns
t_DIST	Setup time, DIN valid to SCLK falling edge	10		10		ns
t_DIHD	Hold time, valid DIN after SCLK falling edge	10		11		ns
t_CSH	Pulse duration, CS high	2		2		t_CLK
t_SCCS	Delay time, final SCLK falling edge to CS high	4		4		t_CLK
t_SDECODE	Command decode time	4		4		t_CLK
t_DISCK2ST	Setup time, DAISY_IN valid to SCLK rising edge	10		10		ns
t_DISCK2HT	Hold time, DAISY_IN valid after SCLK rising edge	10		10		ns

7.7 Switching Characteristics: Serial Interface

over operating ambient temperature range (unless otherwise noted)

PARAMETER		2.7 V ≤ DVDD ≤ 3.6 V		1.8 V ≤ DVDD ≤ 2.0 V		UNIT
PARAMETER		MIN	MAX	MIN	MAX	UNIT
t_DOHD	Hold time, SCLK falling edge to invalid DOUT	10		10		ns
t_DOPD	Propagation delay time, SCLK rising edge to DOUT valid		17		32	ns
t_CSDOD	Propagation delay time, CS low to DOUT driven	10		20		ns
t_CSDOZ	Propagation delay time, CS high to DOUT Hi-Z		10		20	ns

ADS1299 ADS1299-4 ADS1299-6 tim_serial_bas459.gif

NOTE:

SPI settings are CPOL = 0 and CPHA = 1.

Figure 1. Serial Interface Timing

ADS1299 ADS1299-4 ADS1299-6 tim_daisy_bas499.gif

Figure 2. Daisy-Chain Interface Timing

7.8 Typical Characteristics

At T_A = 25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, internal VREFP = 4.5 V, VREFN = AVSS, external clock = 2.048 MHz, data rate = 250 SPS, and gain = 12 (unless otherwise noted)