ZHCS181G August 2011 – April 2021 TPS53355
PRODUCTION DATA
PIN | I/O/P(1) | DESCRIPTION | ||
---|---|---|---|---|
NAME | NO | |||
EN | 2 | I | Enable pin. Typical turn-on threshold voltage is 1.2 V. Typical turn-off threshold is 0.95 V. | |
GND | — | — | Ground and thermal pad of the device. Use proper number of vias to connect to ground plane. | |
LL | 6 | B | Output of converted power. Connect this pin to the output Inductor. | |
7 | ||||
8 | ||||
9 | ||||
10 | ||||
11 | ||||
MODE | 20 | I | Soft-start and Skip/CCM selection. Connect a resistor to select soft-start time using Table 7-3. The soft-start time is detected and stored into internal register during start-up. | |
N/C | 5 | No connect. | ||
PGOOD | 3 | O | Open drain power good flag. Provides 1-ms start-up delay after VFB falls in specified limits. When VFB goes out of the specified limits PGOOD goes low after a 2-µs delay. | |
RF | 22 | I | Switching frequency selection. Connect a resistor to GND or VREG to select switching frequency using Table 7-1. The switching frequency is detected and stored during the startup. | |
TRIP | 21 | I | OCL detection threshold setting pin. ITRIP = 10 µA at room temperature, 4700 ppm/°C current is sourced and set the OCL trip voltage as follows: | |
VOCL = VTRIP/32 | (VTRIP ≤ 2.4 V, VOCL ≤ 75 mV) | |||
VBST | 4 | P | Supply input for high-side FET gate driver (boost terminal). Connect capacitor from this pin to LL node. Internally connected to VREG via bootstrap MOSFET switch. | |
VDD | 19 | P | Controller power supply input. VDD input voltage range is from 4.5 V to 25 V. | |
VFB | 1 | I | Output feedback input. Connect this pin to Vout through a resistor divider. | |
VIN | 12 | P | Conversion power input. VIN input voltage range is from 1.5 V to 15 V. | |
13 | ||||
14 | ||||
15 | ||||
16 | ||||
17 | ||||
VREG | 18 | P | 5-V low drop out (LDO) output. Supplies the internal analog circuitry and driver circuitry. |