ZHCS253A September 2011 – July 2015 TPS61170-Q1
PRODUCTION DATA.
As for all switching power supplies, especially those switching at high frequencies and/or providing high currents, layout is an important design step. If layout is not carefully done, the regulator could suffer from instability as well as noise problems. To maximize efficiency, switch rise and fall times should be as short as possible. To reduce radiation of high-frequency switching noise and harmonics, proper layout of the high-frequency switching path is essential. Minimize the length and area of all traces connected to the SW pin and always use a ground plane under the switching regulator to minimize interplane coupling. The high current path including the switch, Schottky diode, and output capacitor, contains nanosecond rise and fall times and should be kept as short as possible. The input capacitor needs not only to be close to the VIN pin, but also to the GND pin to reduce the IC supply ripple. Figure 20 shows a sample layout.
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation of the TPS61170-Q1. Calculate the maximum allowable dissipation, PD(max), and keep the actual dissipation less than or equal to PD(max). The maximum-power-dissipation limit is determined using Equation 14:
where
The TPS61170-Q1 comes in a thermally enhanced SON package. This package includes a thermal pad that improves the thermal capabilities of the package. The RθJA of the SON package greatly depends on the PCB layout and thermal pad connection. The thermal pad must be soldered to the analog ground on the PCB. Using thermal vias underneath the thermal pad as illustrated in the layout example. Also see the QFN/SON PCB Attachment application report (SLUA271).