ZHCS264E MAY   2011  – July 2018 TPS51206

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化应用
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VTT Sink and Source Regulator
      2. 7.3.2 VTTREF
      3. 7.3.3 VDD Undervoltage Lockout Protection
      4. 7.3.4 VTT Current Limit
      5. 7.3.5 Overtemperature Protection
      6. 7.3.6 Power On and Off Sequence
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power State Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 VLDOIN = VDDQ Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 VDD Capacitor
          2. 8.2.1.2.2 VLDOIN Capacitor
          3. 8.2.1.2.3 VTTREF Capacitor
          4. 8.2.1.2.4 VTT Capacitor
          5. 8.2.1.2.5 VTTSNS Connection
          6. 8.2.1.2.6 VDDQSNS Connection
        3. 8.2.1.3 Application Curves
      2. 8.2.2 VLDOIN Separated from VDDQ Configuration
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息

5 Pin Configuration and Functions

DSQ Package
10-Pin WSON
Top View
TPS51206 pinout_dsq_slusah1.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
GND 8 – Signal ground
PGND 4 – Power GND for VTT LDO
S3 7 I S3 signal input
S5 9 I S5 signal input
VDD 10 I Device power supply input (3.3 V or 5 V)
VDDQSNS 1 I VDDQ sense input, reference input for VTTREF
VLDOIN 2 I Power supply input for VTT/ VTTREF
VTT 3 O Power output for VTT LDO, need to connect 10-μF or greater MLCC for stability. No maximum limit for VTT output capacitance.
VTTREF 6 O VTTREF buffered reference output. Connect to MLCC between 0.22-µF and 1-µF for stability. The VTTREF pin can not be open.
VTTSNS 5 I VTT LDO voltage sense input
Thermal Pad — Solder to the ground plane for increased thermal performance.
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