ZHCS363L
August 2011 – March 2017
TRF7970A
PRODUCTION DATA.
1
器件概述
1.1
特性
1.2
应用范围
1.3
说明
1.4
功能方框图
2
修订历史记录
3
Device Characteristics
3.1
Related Products
4
Terminal Configuration and Functions
4.1
Pin Diagram
4.2
Signal Descriptions
Table 4-1
Terminal Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Electrical Characteristics
5.5
Thermal Resistance Characteristics
5.6
Switching Characteristics
6
Detailed Description
6.1
Overview
6.1.1
RFID and NFC Operation – Reader and Writer
6.1.2
NFC Device Operation – Initiator
6.1.3
NFC Device Operation – Target
6.1.3.1
Active Target
6.1.3.2
Passive Target
6.1.3.3
Card Emulation
6.2
System Block Diagram
6.3
Power Supplies
6.3.1
Supply Arrangements
6.3.2
Supply Regulator Settings
6.3.3
Power Modes
6.4
Receiver – Analog Section
6.4.1
Main and Auxiliary Receivers
6.4.2
Receiver Gain and Filter Stages
6.5
Receiver – Digital Section
6.5.1
Received Signal Strength Indicator (RSSI)
6.5.1.1
Internal RSSI – Main and Auxiliary Receivers
6.5.1.2
External RSSI
6.6
Oscillator Section
6.7
Transmitter – Analog Section
6.8
Transmitter – Digital Section
6.9
Transmitter – External Power Amplifier and Subcarrier Detector
6.10
TRF7970A IC Communication Interface
6.10.1
General Introduction
6.10.1.1
Continuous Address Mode
6.10.1.2
Noncontinuous Address Mode (Single Address Mode)
6.10.1.3
Direct Command Mode
6.10.1.4
FIFO Operation
6.10.2
Parallel Interface Mode
6.10.3
Reception of Air Interface Data
6.10.4
Data Transmission From MCU to TRF7970A
6.10.5
Serial Interface Communication (SPI)
6.10.5.1
Serial Interface Mode With Slave Select (SS)
6.10.6
Direct Mode
6.11
TRF7970A Initialization
6.12
Special Direct Mode for Improved MIFARE Compatibility
6.13
NFC Modes
6.13.1
Target
6.13.2
Initiator
6.14
Direct Commands from MCU to Reader
6.14.1
Command Codes
6.14.1.1
Idle (0x00)
6.14.1.2
Software Initialization (0x03)
6.14.1.3
Initial RF Collision Avoidance (0x04)
6.14.1.4
Response RF Collision Avoidance (0x05)
6.14.1.5
Response RF Collision Avoidance (0x06, n = 0)
6.14.1.6
Reset FIFO (0x0F)
6.14.1.7
Transmission With CRC (0x11)
6.14.1.8
Transmission Without CRC (0x10)
6.14.1.9
Delayed Transmission With CRC (0x13)
6.14.1.10
Delayed Transmission Without CRC (0x12)
6.14.1.11
Transmit Next Time Slot (0x14)
6.14.1.12
Block Receiver (0x16)
6.14.1.13
Enable Receiver (0x17)
6.14.1.14
Test Internal RF (RSSI at RX Input With TX ON) (0x18)
6.14.1.15
Test External RF (RSSI at RX Input with TX OFF) (0x19)
6.15
Register Description
6.15.1
Register Preset
6.15.2
Register Overview
6.15.3
Detailed Register Description
6.15.3.1
Main Configuration Registers
6.15.3.1.1
Chip Status Control Register (0x00)
6.15.3.1.2
ISO Control Register (0x01)
6.15.3.2
Control Registers – Sublevel Configuration Registers
6.15.3.2.1
ISO/IEC 14443 TX Options Register (0x02)
6.15.3.2.2
ISO/IEC 14443 High-Bit-Rate and Parity Options Register (0x03)
6.15.3.2.3
TX Timer High Byte Control Register (0x04)
6.15.3.2.4
TX Timer Low Byte Control Register (0x05)
6.15.3.2.5
TX Pulse Length Control Register (0x06)
6.15.3.2.6
RX No Response Wait Time Register (0x07)
6.15.3.2.7
RX Wait Time Register (0x08)
6.15.3.2.8
Modulator and SYS_CLK Control Register (0x09)
6.15.3.2.9
RX Special Setting Register (0x0A)
6.15.3.2.10
Regulator and I/O Control Register (0x0B)
6.15.3.3
Status Registers
6.15.3.3.1
IRQ Status Register (0x0C)
6.15.3.3.2
Interrupt Mask Register (0x0D) and Collision Position Register (0x0E)
6.15.3.3.3
RSSI Levels and Oscillator Status Register (0x0F)
6.15.3.3.4
Special Functions Register (0x10)
6.15.3.3.5
Special Functions Register (0x11)
6.15.3.3.6
Adjustable FIFO IRQ Levels Register (0x14)
6.15.3.3.7
NFC Low Field Level Register (0x16)
6.15.3.3.8
NFCID1 Number Register (0x17)
6.15.3.3.9
NFC Target Detection Level Register (0x18)
6.15.3.3.10
NFC Target Protocol Register (0x19)
6.15.3.4
Test Registers
6.15.3.4.1
Test Register (0x1A)
6.15.3.4.2
Test Register (0x1B)
6.15.3.5
FIFO Control Registers
6.15.3.5.1
FIFO Status Register (0x1C)
6.15.3.5.2
TX Length Byte1 Register (0x1D), TX Length Byte2 Register (0x1E)
7
Applications, Implementation, and Layout
7.1
TRF7970A Reader System Using SPI With SS Mode
7.1.1
General Application Considerations
7.1.2
Schematic
7.2
Layout Considerations
7.3
Impedance Matching TX_Out (Pin 5) to 50 Ω
7.4
Reader Antenna Design Guidelines
8
器件和文档支持
8.1
入门和下一步
8.2
器件命名规则
8.3
工具与软件
8.4
文档支持
8.5
社区资源
8.6
商标
8.7
静电放电警告
8.8
Glossary
9
机械、封装和可订购信息
1.1
特性
支持近场通信 (NFC) 标准 NFCIP-1 (ISO/IEC 18092) 和 NFCIP‑2 (ISO/IEC 21481)
完全集成了以下标准的协议处理:ISO/IEC 15693、ISO/IEC 18000-3、ISO/IEC 14443 A 和 B 以及 FeliCa™
集成式编码器、解码器和数据组帧功能,用于 NFC 发起方运行模式以及有源和无源目标方运行模式,适合所有三种比特率(106kbps、212kbps、424kbps)以及卡仿真
借助带有可编程唤醒电平的射频场检测器,实现 NFC 无源应答器仿真
通过射频场检测器避免 NFC 物理碰撞
通过集成的状态机实现 ISO/IEC 14443 A 防撞(破坏的字节)
(应答器仿真或 NFC 无源目标)
输入电压范围:2.7VDC 至 5.5VDC
可编程输出功率:+20dBm (100mW),+23dBm (200mW)
从 1.8VDC 至 5.5 VDC 的可编程 I/O 电压电平
来自 13.56MHz 或者 27.12MHz 晶振或者振荡器的可编程系统时钟频率输出 (RF,RF/2,RF/4)
针对其它系统组件(微控制器 (MCU),外设,指示器)的集成电压稳压器输出,20mA(最大值)
可编程调制深度
具有针对“读取漏洞”消除和邻近读取器系统或者周围环境频带内噪声检测的具有接收信号强度指示器 (RSSI) 的双接收器架构
针对超低功耗系统设计的可编程功率模式(断电时 < 1µA)
并行或 SPI 接口(带有 127 字节 FIFO)
温度范围:-40°C 至 110°C
32 引脚 QFN 封装 (5mm × 5mm)
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