6.10.5 Serial Interface Communication (SPI)

When an SPI interface is used, I/O pins I/O_2, I/O_1, and I/O_0 must be hard wired according to Table 6-10. On power up, the TRF7970A looks for the status of these pins and then enters into the corresponding mode.

The serial communications work in the same manner as the parallel communications with respect to the FIFO, except for the following condition. On receiving an IRQ from the reader, the MCU reads the TRF7970A IRQ Status register to determine how to service the reader. After this, the MCU must to do a dummy read to clear the reader's IRQ status register. The dummy read is required in SPI mode because the reader's IRQ status register needs an additional clock cycle to clear the register. This is not required in parallel mode because the additional clock cycle is included in the Stop condition. When first establishing communications with the TRF7970A, the SOFT_INIT (0x03) and IDLE (0x00) commands should be sent first from the MCU (see Table 6-19).

The procedure for a dummy read is as follows (see Figure 6-17 and Figure 6-18):

1. Start the dummy read:
   1. When using slave select (SS): set SS bit low.
   2. When not using SS: start condition is when Data Clock is high (see Table 6-10).
2. Send address word to IRQ status register (0x0C) with read and continuous address mode bits set to 1 (see Table 6-10).
3. Read 1 byte (8 bits) from IRQ status register (0x0C).
4. Dummy-read 1 byte from register 0x0D (collision position and interrupt mask).
5. Stop the dummy read:
   1. When using slave select (SS): set SS bit high.
   2. When not using SS: stop condition when Data Clock is high.

Figure 6-17 Procedure for Dummy Read

Figure 6-18 Example of Dummy Read Using SPI With SS